公开(公告)号：US20200177173A1

公开(公告)日：2020-06-04

申请号：US16786364

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wanghua WU ,  Chih-Wei YAO

IPC: H03K5/156 ,  H03L7/099 ,  H03L7/097 ,  H04L25/49 ,  H03L7/08 ,  H03L7/091

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.