公开(公告)号：US20250024665A1

公开(公告)日：2025-01-16

申请号：US18584646

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jin LEE ,  Sung Won YOO ,  Won Sok LEE ,  Min Hee CHO ,  Si Yeon CHO

IPC: H10B12/00

Abstract: The semiconductor memory device including a bit line in a first direction on a substrate, a channel structure on the bit line, and including a first vertical part in a second direction, and a second vertical part apart from the first vertical part in the first direction and in the second direction, a back-gate electrode on the bit line on a side of the channel structure and in the second direction, a back-gate insulating film between the back-gate electrode and the channel structure, a back-gate capping film on the back-gate electrode and the back-gate insulating film, a first and second word lines between the first and the second vertical parts and in the second direction, the second word line spaced apart from the first word line in the first direction and first and second capacitors connected to the first and second vertical parts, on the first and second vertical parts.

公开(公告)号：US20220223732A1

公开(公告)日：2022-07-14

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H01L27/108

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20240371994A1

公开(公告)日：2024-11-07

申请号：US18775518

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.