公开(公告)号：US20240357810A1

公开(公告)日：2024-10-24

申请号：US18757708

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Il Gweon KIM ,  Hyun Cheol KIM ,  Hyeoung Won SEO ,  Sung Won YOO ,  Jae Ho HONG

IPC: H10B43/20 ,  H10B43/10

CPC classification number: H10B43/20 ,  H10B43/10

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

公开(公告)号：US20220139948A1

公开(公告)日：2022-05-05

申请号：US17377848

申请日：2021-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Il Gweon KIM ,  Hyun Cheol KIM ,  Hyeoung Won SEO ,  Sung Won YOO ,  Jae Ho HONG

IPC: H01L27/11578 ,  H01L27/11565

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

公开(公告)号：US20210335798A1

公开(公告)日：2021-10-28

申请号：US17227793

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Hyun Cheol KIM ,  Satoru YAMADA ,  Sung Won YOO ,  Jae Ho HONG

IPC: H01L27/1156 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11551

Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

公开(公告)号：US20250024665A1

公开(公告)日：2025-01-16

申请号：US18584646

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jin LEE ,  Sung Won YOO ,  Won Sok LEE ,  Min Hee CHO ,  Si Yeon CHO

IPC: H10B12/00

Abstract: The semiconductor memory device including a bit line in a first direction on a substrate, a channel structure on the bit line, and including a first vertical part in a second direction, and a second vertical part apart from the first vertical part in the first direction and in the second direction, a back-gate electrode on the bit line on a side of the channel structure and in the second direction, a back-gate insulating film between the back-gate electrode and the channel structure, a back-gate capping film on the back-gate electrode and the back-gate insulating film, a first and second word lines between the first and the second vertical parts and in the second direction, the second word line spaced apart from the first word line in the first direction and first and second capacitors connected to the first and second vertical parts, on the first and second vertical parts.

公开(公告)号：US20210319293A1

公开(公告)日：2021-10-14

申请号：US17224575

申请日：2021-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan LEE ,  Yong Seok KIM ,  Hyun Cheol KIM ,  Satoru YAMADA ,  Sung Won YOO ,  Jae Ho HONG

IPC: G06N3/063 ,  G11C13/00 ,  G06N3/04 ,  G11C11/54

Abstract: A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.