公开(公告)号：US09997525B2

公开(公告)日：2018-06-12

申请号：US15398090

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Hojun Seong ,  Bongtae Park ,  Woo-Jung Kim

IPC: H01L29/788 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11529 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11573

Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.