公开(公告)号：US20240040792A1

公开(公告)日：2024-02-01

申请号：US18356324

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngshik Yun ,  Dongsik Lee ,  Siwan Kim ,  Sori Lee ,  Bongtae Park ,  Jaejoo Shim

IPC: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/04 ,  H01L23/528 ,  H10B80/00 ,  H01L25/065

CPC classification number: H10B43/40 ,  H10B43/27 ,  H10B43/35 ,  H10B41/40 ,  H10B41/27 ,  H10B41/35 ,  G11C16/0483 ,  H01L23/5283 ,  H10B80/00 ,  H01L25/0652 ,  H01L2225/06541

Abstract: A semiconductor device includes a peripheral circuit region and a memory cell region. The memory cell region may include a stack structure including gate electrodes and interlayer insulating layers repeatedly and alternately stacked in a vertical direction, and a channel structure penetrating through the stack structure. The gate electrodes may include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes. Each of the first gate electrodes may have a first thickness. Each of the second gate electrodes may have a second thickness that is greater than the first thickness. Each of the third gate electrodes may have a third thickness that is smaller than the second thickness.

公开(公告)号：US09553098B2

公开(公告)日：2017-01-24

申请号：US14858756

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US09171853B2

公开(公告)日：2015-10-27

申请号：US14200610

申请日：2014-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US11637110B2

公开(公告)日：2023-04-25

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US20220415915A1

公开(公告)日：2022-12-29

申请号：US17747462

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN HWANG ,  Jaejoo Shim ,  Bongtae Park ,  Taechul Jung ,  Jongyoon Choi

IPC: H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: Semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, separation regions penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, channel structures arranged in columns in the third direction and rows in the second direction and penetrating the gate electrodes between the separation regions, and bit lines extending in the third direction on the channel structures. The channel structures include a first group of channel structures repeatedly arranged and including three columns arranged with a first pitch and a second pitch smaller than the first pitch in order, and the bit lines are arranged with at least one pitch smaller than the second pitch in the second direction.

公开(公告)号：US09997525B2

公开(公告)日：2018-06-12

申请号：US15398090

申请日：2017-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Hojun Seong ,  Bongtae Park ,  Woo-Jung Kim

IPC: H01L29/788 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11529 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11573

Abstract: A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.

公开(公告)号：US11233062B2

公开(公告)日：2022-01-25

申请号：US16827778

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

公开(公告)号：US10784281B2

公开(公告)日：2020-09-22

申请号：US16425349

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Heon Kang ,  Bongtae Park ,  Jae-Joo Shim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157

Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.

公开(公告)号：US20200135756A1

公开(公告)日：2020-04-30

申请号：US16425349

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Heon KANG ,  Bongtae Park ,  Jae-Joo Shim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02

Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.