公开(公告)号：US20250149494A1

公开(公告)日：2025-05-08

申请号：US18940264

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyung Yoo ,  Jinwoo Park ,  Kyonghwan Koh ,  Woohyeong Kim ,  Taeryong Kim

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer that fills a center portion of a space between the first substrate and the first semiconductor chip, and a first molding member that covers an upper surface and side surfaces of the first semiconductor chip, and fills a periphery portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

公开(公告)号：US20240088092A1

公开(公告)日：2024-03-14

申请号：US18462610

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Woohyeong Kim ,  Jinwoo Park ,  Jayeon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.