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公开(公告)号:US20250125197A1
公开(公告)日:2025-04-17
申请号:US18884732
申请日:2024-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junyun Kweon , Wooju Kim , Junho Yoon , Dayoung Cho , Jinwook Hong
IPC: H01L21/78 , B23K26/38 , B23K101/40 , H01L21/02 , H01L21/304 , H01L21/683
Abstract: A semiconductor chip includes a base substrate including a first surface, a second surface opposite to the first surface, and a sidewall extending between the first surface and the second surface, and a device layer on the first surface of the base substrate, wherein the base substrate includes a stress relief region within a first depth from the second surface and a second depth from the sidewall, and at least a portion of the sidewall of the base substrate is recessed inward from the sidewall of the device layer.
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公开(公告)号:US20240387460A1
公开(公告)日:2024-11-21
申请号:US18320553
申请日:2023-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Heejae NAM , Junyun Kweon , Wooju Kim , Junggeun Shin
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538
Abstract: A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.
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公开(公告)号:US20230395547A1
公开(公告)日:2023-12-07
申请号:US18205329
申请日:2023-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junyun Kweon , Yeongbeom Ko , Wooju Kim , Jungseok Ryu , Junho Yoon , Hwayoung Lee
CPC classification number: H01L24/08 , H10B80/00 , H01L2224/08145
Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.
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公开(公告)号:US12015005B2
公开(公告)日:2024-06-18
申请号:US17537994
申请日:2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yeongbeom Ko , Wooju Kim , Heejae Nam , Jungseok Ryu , Haemin Park
IPC: H01L23/00 , H01L25/065 , H01L25/18
CPC classification number: H01L24/32 , H01L25/0657 , H01L24/73 , H01L25/18 , H01L2224/32057 , H01L2224/32058 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2924/10156
Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.
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