SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

    公开(公告)号:US20240387460A1

    公开(公告)日:2024-11-21

    申请号:US18320553

    申请日:2023-05-19

    Abstract: A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20230395547A1

    公开(公告)日:2023-12-07

    申请号:US18205329

    申请日:2023-06-02

    CPC classification number: H01L24/08 H10B80/00 H01L2224/08145

    Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

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