公开(公告)号：US20160225633A1

公开(公告)日：2016-08-04

申请号：US14967455

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Yeon ho Park ,  Wookhyun Kwon ,  Nakjin Son

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and intermediate mold layers on a substrate, forming first upper mold patterns and first spacers on the first and second regions, respectively, of the substrate, etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively, forming second spacers to cover sidewalls of the first and second intermediate mold patterns, etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns, and etching the substrate using the lower mold patterns as an etch mask to form active patterns.

Abstract translation: 提供制造包括场效应晶体管的半导体器件的方法。 这样的方法可以包括在衬底上顺序地形成下模层和中间模层，分别在衬底的第一和第二区上形成第一上模模和第一衬垫，使用第一上模模蚀刻中间模层， 间隔物作为蚀刻掩模，以分别形成第一和第二中间模具图案，形成第二间隔件以覆盖第一和第二中间模具图案的侧壁;使用第二间隔件蚀刻下模具层以形成下模具图案; 并使用下模具图案蚀刻基板作为蚀刻掩模以形成有源图案。

公开(公告)号：US12211760B2

公开(公告)日：2025-01-28

申请号：US17837453

申请日：2022-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Wookhyun Kwon ,  Hyoeun Park ,  Kangill Seo

IPC: H01L21/66

Abstract: Integrated circuit devices may include a cell transistor and a parameter measuring structure (e.g., a resistance measuring structure). The cell transistor may be on a first surface of a substrate structure, which is opposite a second surface thereof. The parameter measuring structure may include first and second contact structures that extend through the substrate structure. The second surface of the substrate structure may expose respective portions of the first and second contact structures.

公开(公告)号：US09911828B2

公开(公告)日：2018-03-06

申请号：US14967455

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Yeon ho Park ,  Wookhyun Kwon ,  Nakjin Son

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and intermediate mold layers on a substrate, forming first upper mold patterns and first spacers on the first and second regions, respectively, of the substrate, etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively, forming second spacers to cover sidewalls of the first and second intermediate mold patterns, etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns, and etching the substrate using the lower mold patterns as an etch mask to form active patterns.

公开(公告)号：US20230411353A1

公开(公告)日：2023-12-21

申请号：US17969402

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Wookhyun Kwon ,  Jaehong Lee

IPC: H01L25/065 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L23/5286 ,  H01L27/0259 ,  H01L27/0688

Abstract: A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.

公开(公告)号：US20230326813A1

公开(公告)日：2023-10-12

申请号：US17837453

申请日：2022-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Wookhyun Kwon ,  Hyoeun Park ,  Kangill Seo

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: Integrated circuit devices may include a cell transistor and a parameter measuring structure (e.g., a resistance measuring structure). The cell transistor may be on a first surface of a substrate structure, which is opposite a second surface thereof. The parameter measuring structure may include first and second contact structures that extend through the substrate structure. The second surface of the substrate structure may expose respective portions of the first and second contact structures.