公开(公告)号：US12274092B2

公开(公告)日：2025-04-08

申请号：US18406345

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Myunggil Kang ,  Kang-Ill Seo

IPC: H10D86/00 ,  G01R27/02 ,  H01L21/66 ,  H01L23/535 ,  H10D30/67 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D88/00

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US12249603B2

公开(公告)日：2025-03-11

申请号：US17570920

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Inchan Hwang ,  Hyoeun Park ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L25/07 ,  H01L27/07 ,  H01L27/08 ,  H01L49/02

Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

公开(公告)号：US11935922B2

公开(公告)日：2024-03-19

申请号：US17970777

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US11843001B2

公开(公告)日：2023-12-12

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Ki-Il Kim ,  Gunho Jo ,  Kang-Ill Seo

IPC: H04L45/745 ,  H04L12/46 ,  H04L45/52 ,  H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20230326858A1

公开(公告)日：2023-10-12

申请号：US17887203

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buhyun HAM ,  Byounghak Hong ,  Myunghoon Jung ,  Wonhyuk Hong ,  Seungyoung Lee ,  Kang-ill Seo

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/76897

Abstract: Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.

公开(公告)号：US20230049816A1

公开(公告)日：2023-02-16

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOYOUNG PARK ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US11502167B2

公开(公告)日：2022-11-15

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US11355640B1

公开(公告)日：2022-06-07

申请号：US17167640

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A hybrid multi-stack semiconductor device and a method of manufacturing the same are provided. The hybrid multi-stack semiconductor device includes a nanosheet stack and a fin field-effect transistor (finFET) stack formed above the nanosheet stack, wherein the nanosheet stack includes a plurality of nanosheet layers formed above a substrate and enclosed by a 1st gate structure, wherein the at least one fin structure has a self-aligned form with respect to the nanosheet stack so that a left horizontal distance between a leftmost side surface of the at least one fin structure and a left side surface of the nanosheet stack is equal to a right horizontal distance between a rightmost side surface of the at least one fin structure and a right side surface of the nanosheet stack.

公开(公告)号：US20250107201A1

公开(公告)日：2025-03-27

申请号：US18972067

申请日：2024-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang-ill Seo ,  Daewon Ha ,  Jason Martineau

IPC: H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.

公开(公告)号：US20250107172A1

公开(公告)日：2025-03-27

申请号：US18974171

申请日：2024-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.