公开(公告)号：US12125788B2

公开(公告)日：2024-10-22

申请号：US18386497

申请日：2023-11-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Saehan Park ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L27/06

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0694 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

摘要： Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US12087815B2

公开(公告)日：2024-09-10

申请号：US18187506

申请日：2023-03-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hwichan Jun ,  Inchan Hwang ,  Byounghak Hong

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/0665 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US12057448B2

公开(公告)日：2024-08-06

申请号：US18356545

申请日：2023-07-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

摘要： A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US20230420459A1

公开(公告)日：2023-12-28

申请号：US18056181

申请日：2022-11-16

申请人： Samsung Electronics Co., Ltd.

发明人： Byounghak Hong ,  Sooyoung Park ,  Jaehong Lee ,  Kang-ill Seo ,  WookHyun Kwon

IPC分类号： H01L27/092 ,  H01L27/06 ,  H01L21/768

CPC分类号： H01L27/0922 ,  H01L27/0688 ,  H01L21/768

摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate and a transistor stack on the substrate. The transistor stack comprises a first transistor and a second transistor stacked in a first direction. The first transistor comprises first and second source/drain regions and a first channel region between the first and second source/drain regions, and the first source/drain region comprises a first metal layer. The second transistor comprises third and fourth source/drain regions and a second channel region between the third and fourth source/drain regions, and the first and third source/drain regions overlap each other in the first direction. The transistor stack further comprises a metal interconnector contacting the third source/drain region and the first metal layer of the first source/drain region material.

公开(公告)号：US11735585B2

公开(公告)日：2023-08-22

申请号：US17223829

申请日：2021-04-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

摘要： A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11664433B2

公开(公告)日：2023-05-30

申请号：US17366534

申请日：2021-07-02

申请人： Samsung Electronics Co., Ltd.

发明人： Byounghak Hong ,  Seunghyun Song ,  Inchan Hwang

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L29/41775 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0665

摘要： Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

公开(公告)号：US12040327B2

公开(公告)日：2024-07-16

申请号：US17500618

申请日：2021-10-13

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Inchan Hwang ,  Seunghyun Song ,  Byounghak Hong

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

公开(公告)号：US20240063123A1

公开(公告)日：2024-02-22

申请号：US18386497

申请日：2023-11-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Saehan PARK ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC分类号： H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

CPC分类号： H01L23/5286 ,  H01L27/0694 ,  H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/53257

摘要： Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US20230411353A1

公开(公告)日：2023-12-21

申请号：US17969402

申请日：2022-10-19

申请人： Samsung Electronics Co., Ltd.

发明人： Byounghak Hong ,  Wookhyun Kwon ,  Jaehong Lee

IPC分类号： H01L25/065 ,  H01L23/528 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L25/0657 ,  H01L23/5286 ,  H01L27/0259 ,  H01L27/0688

摘要： A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.

公开(公告)号：US20230335549A1

公开(公告)日：2023-10-19

申请号：US17866343

申请日：2022-07-15

申请人： Samsung Electronics Co., Ltd.

发明人： Inchan Hwang ,  Jaejik Baek ,  Byounghak Hong ,  Saehan Park ,  Kang-ill Seo

IPC分类号： H01L21/822 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L29/66545 ,  H01L29/6656

摘要： An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.