公开(公告)号：US20230361119A1

公开(公告)日：2023-11-09

申请号：US18134853

申请日：2023-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYEN-HEE LEE ,  Kyungsoo Kim

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/822 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed are three-dimensional semiconductor devices and their fabrication methods. The 3D semiconductor device includes a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region above the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, at least one gate electrode on the lower and upper channel patterns, a first active contact electrically connected to the lower source/drain pattern, and a second active contact electrically connected to the upper source/drain pattern. A first central line of the lower source/drain pattern and a second central line of the upper source/drain pattern in a vertical direction are offset from each other in a first direction perpendicular to the vertical direction. The first active contact and the second active contact are spaced apart from each other in the first direction.

公开(公告)号：US20250156078A1

公开(公告)日：2025-05-15

申请号：US19024764

申请日：2025-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F3/06

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US12236098B2

公开(公告)日：2025-02-25

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US12079146B2

公开(公告)日：2024-09-03

申请号：US17383056

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon Cho ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jonghoon Kim ,  Jonghyun Seok ,  Jonggeon Lee

IPC: H05K1/02 ,  G06F1/20 ,  G06F1/30 ,  G06F13/12 ,  G06F13/16 ,  G06F13/364 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/36 ,  H05K7/02 ,  H05K7/20

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/409 ,  G11C5/06 ,  G11C7/1063

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.

公开(公告)号：US20230165016A1

公开(公告)日：2023-05-25

申请号：US17934317

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae Lee ,  Kyungsoo Kim ,  Jinyoung Park ,  Kyen-Hee Lee

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L27/228 ,  H01L43/04 ,  H01L43/06

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.

公开(公告)号：US20220027090A1

公开(公告)日：2022-01-27

申请号：US17154030

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F3/06 ,  G06F1/08

Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

公开(公告)号：US09911828B2

公开(公告)日：2018-03-06

申请号：US14967455

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Yeon ho Park ,  Wookhyun Kwon ,  Nakjin Son

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and intermediate mold layers on a substrate, forming first upper mold patterns and first spacers on the first and second regions, respectively, of the substrate, etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively, forming second spacers to cover sidewalls of the first and second intermediate mold patterns, etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns, and etching the substrate using the lower mold patterns as an etch mask to form active patterns.

公开(公告)号：US20250165153A1

公开(公告)日：2025-05-22

申请号：US19029486

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US20240394331A1

公开(公告)日：2024-11-28

申请号：US18608453

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu PARK ,  Kyungsoo Kim ,  Nayeon Kim ,  Jinin So ,  Kyoungwan Woo ,  Younghyun Lee ,  Jong-Geon Lee ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F17/16 ,  G06F7/501 ,  G06F13/42

Abstract: A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.

公开(公告)号：US11620135B2

公开(公告)日：2023-04-04

申请号：US17115924

申请日：2020-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggeon Lee ,  Kyungsoo Kim ,  Jinin So ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F9/00 ,  G06F9/4401 ,  G06N20/00

Abstract: A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.