公开(公告)号：US20240266344A1

公开(公告)日：2024-08-08

申请号：US18422924

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Changbeom Kim ,  Jungho Do ,  Wookyu Kim

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.

公开(公告)号：US11509295B2

公开(公告)日：2022-11-22

申请号：US17340215

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang ,  Changbeom Kim ,  Dalhee Lee ,  Wookyu Kim

IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/3562

Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.