公开(公告)号：US20220384449A1

公开(公告)日：2022-12-01

申请号：US17735838

申请日：2022-05-03

申请人： Samsung Electronics Co., Ltd.

发明人： EUNJUNG KIM ,  HYO-SUB KIM ,  JAY-BOK CHOI ,  YONGSEOK AHN ,  JUNHYEOK AHN ,  KISEOK LEE ,  MYEONG-DONG LEE ,  YOONYOUNG CHOI

IPC分类号： H01L27/108

摘要： A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

公开(公告)号：US20210036101A1

公开(公告)日：2021-02-04

申请号：US16947090

申请日：2020-07-17

申请人： Samsung Electronics Co., Ltd.

发明人： YOONYOUNG CHOI ,  BYUNGHYUN LEE ,  BYEONGJOO KU ,  SEUNGJIN KIM ,  SANGJAE PARK ,  JINWOO BAE ,  HANGEOL LEE ,  BOWO CHOI ,  HYUNSIL HONG

IPC分类号： H01L49/02

摘要： Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

公开(公告)号：US20220020758A1

公开(公告)日：2022-01-20

申请号：US17192086

申请日：2021-03-04

申请人： Samsung Electronics Co., Ltd.

发明人： SEORYONG PARK ,  SEUNGUK HAN ,  Jiyoung AHN ,  Kiseok LEE ,  YOONYOUNG CHOI ,  JISEOK HONG

IPC分类号： H01L27/11551 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11578 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

公开(公告)号：US20210151439A1

公开(公告)日：2021-05-20

申请号：US16908833

申请日：2020-06-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： YOONYOUNG CHOI ,  Byunghyun Lee ,  Seungjin Kim ,  Byeongjoo Ku ,  Sangjae Park ,  Hangeol Lee

IPC分类号： H01L27/108 ,  H01L23/532 ,  H01L21/768

摘要： A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.