公开(公告)号：US20240340012A1

公开(公告)日：2024-10-10

申请号：US18624590

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BAEKMIN LIM ,  GYUSIK KIM ,  SEUNGJIN KIM ,  SEUNGHYUN OH

IPC: H03L7/081 ,  H03L7/093

CPC classification number: H03L7/081 ,  H03L7/093

Abstract: A clock generation device includes a delay line that generates a modulated clock signal from a reference clock signal having a first period, a pulse generator configured to receive the modulated clock signal and generate a pulse signal in response to edges of pulses included in the modulated clock signal, and a clock generator that generates a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal. The delay line generates a first pulse based on the reference clock signal and then generates a second pulse after a time modulated from the first period by a result of multiplying the second period by a first numerical value selected from a plurality of numerical values according to a certain probability.

公开(公告)号：US20210036101A1

公开(公告)日：2021-02-04

申请号：US16947090

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOONYOUNG CHOI ,  BYUNGHYUN LEE ,  BYEONGJOO KU ,  SEUNGJIN KIM ,  SANGJAE PARK ,  JINWOO BAE ,  HANGEOL LEE ,  BOWO CHOI ,  HYUNSIL HONG

IPC: H01L49/02

Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

公开(公告)号：US20220360270A1

公开(公告)日：2022-11-10

申请号：US17734693

申请日：2022-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGDON JUNG ,  GYUSIK KIM ,  SEUNGJIN KIM ,  SEUNGHYUN OH ,  JIHWAN KIM

IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099

Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

公开(公告)号：US20170093407A1

公开(公告)日：2017-03-30

申请号：US15229499

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGJIN KIM ,  Jihyun KIM ,  Taeik KIM

IPC: H03L7/08 ,  H02M3/07 ,  H03L7/093 ,  G06F1/10 ,  H03L7/099 ,  H03K5/26

CPC classification number: H03L7/0802 ,  G06F1/10 ,  H02M3/07 ,  H03K5/26 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.