公开(公告)号：US20170062468A1

公开(公告)日：2017-03-02

申请号：US15189205

申请日：2016-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWAN SON ,  YOUNG-WOO PARK ,  JAE-DUK LEE

IPC: H01L27/115 ,  G11C16/26 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

Abstract translation: 具有垂直结构的非易失性存储器件包括：衬底上的第一层间绝缘层; 设置在所述第一层间绝缘层上的第一栅电极; 第二层间绝缘层和交替层叠在第一栅电极上的第二栅电极; 穿过所述第一栅电极，所述第二层间绝缘层和所述第二栅电极的开口部分，并暴露所述第一层间绝缘层; 覆盖所述开口部的侧壁和底面的栅介质层; 以及沟道区，形成在所述栅极电介质层上，并且穿透所述栅极电介质层和所述第一层间绝缘层的底表面，从而电连接到所述衬底，其中所述栅极电介质层的侧壁之间的间隔距离在区域 与第一栅电极接触的区域大于与第二栅电极接触的区域。

公开(公告)号：US20190333925A1

公开(公告)日：2019-10-31

申请号：US16505266

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWAN SON ,  JAE-HOON JANG ,  JEE-HOON HAN

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11529

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US20190326316A1

公开(公告)日：2019-10-24

申请号：US16209323

申请日：2018-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HWAN SON ,  Kohji Kanamori ,  Shin-Hwan Kang ,  Young Jin Kwon

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.