公开(公告)号：US20140312961A1

公开(公告)日：2014-10-23

申请号：US14249408

申请日：2014-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGHUN SEO

IPC: G05F1/46

CPC classification number: G11C7/04 ,  G11C5/147 ,  G11C11/4074 ,  G11C29/021 ,  G11C29/023 ,  G11C2029/0409

Abstract: A semiconductor device comprises a metal oxide semiconductor (MOS) transistor circuit configured to receive a body bias voltage, and a negative bias temperature instability compensation (NBTIC) circuit configured to measure a negative bias temperature instability level on the MOS transistor circuit using an operating timing variation measuring unit and to adaptively compensate for a bias according to the measured value.

Abstract translation: 半导体器件包括被配置为接收体偏置的金属氧化物半导体（MOS）晶体管电路和负偏压温度不稳定性补偿（NBTIC）电路，其被配置为使用操作定时来测量MOS晶体管电路上的负偏压温度不稳定电平 变化测量单元，并根据测量值自适应地补偿偏差。

公开(公告)号：US20240170043A1

公开(公告)日：2024-05-23

申请号：US18388569

申请日：2023-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGIL LEE ,  YOUNGHUN SEO

IPC: G11C11/4074 ,  G05F1/575 ,  G11C11/4091

CPC classification number: G11C11/4074 ,  G05F1/575 ,  G11C11/4091 ,  H03K19/20

Abstract: A voltage generator including an LDO (low dropout) regulator that supplies a current to an internal voltage node of a sense amplification circuit as feedback control based on a voltage level of the internal voltage node; and a power switch circuit including a plurality of power switches each having one end connected to an external voltage and an opposite end connected to the internal voltage node, and that supplies the current to the internal voltage node as feed-forward control based on a known number of sense amplifiers to be activated. The voltage generator may efficiently supply current according to an operation mode of the sense amplification circuit.

公开(公告)号：US20240161810A1

公开(公告)日：2024-05-16

申请号：US18381115

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG-JUN LEE ,  YOUNGHUN SEO ,  Hoseok Lee

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G11C11/4097

Abstract: A memory device includes a memory cell array which includes a plurality of word lines and a plurality of bit lines; a plurality of column selection lines which extends over the memory cell array and includes a first part of the memory cell array and a second part connected to the first part; a plurality of bit line sense amplifiers each connected to a bit line and configured to sense data stored in a memory cell; a plurality of local sense amplifiers each configured to output the sensed data from one of the bit line sense amplifiers through a column selection transistor connected to a local column selection line; a control logic circuit which generates a row address signal indicating an activation word line and a column address signal indicating an activation bit line; and a column decoder which activates a column selection line based on the column address signal.

公开(公告)号：US20150036444A1

公开(公告)日：2015-02-05

申请号：US14264466

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGHUN SEO

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C2207/002

Abstract: A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. It further comprises a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal.

Abstract translation: 感测放大器包括：感测放大单元，被配置为连接到位线和存储器件的互补位线，以响应于第一和第二控制信号感测位线的电压变化，并且控制感测位线的电压;以及 基于检测到的电压变化的补偿感测位线。 它还包括第一隔离开关，其被配置为响应于隔离信号将位线与感测位线相连接;第二隔离开关，被配置为响应于隔离信号将互补位线与互补感测位线连接;第一偏移消除开关 被配置为响应于偏移消除信号而将位线与感测位线连接，以及第二偏移消除开关，其被配置为响应于偏移消除信号将互补位线与互补感测位线相连接。