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1.发明授权Nonvolatile memory device including sudden power off detection circuit and sudden power off detection method thereof 有权非易失性存储装置，包括突然断电检测电路和突然断电检测方法公开(公告)号：US08873328B2
公开(公告)日：2014-10-28
申请号：US14037544
申请日：2013-09-26
发明人： Yong Shik Shin , Yunseok Yang , Oh-Seong Kwon
CPC分类号： G11C11/1697 , G11C5/143 , G11C11/1675
摘要： A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.
摘要翻译： 非易失性存储器件包括存储单元阵列，其包括连接到位线和字线的存储单元; 字线解码器，被配置为将字线电压施加到所述字线; 配置为选择位线的至少一个位线的位线选择器; 控制逻辑，被配置为控制字线解码器和位线选择器，使得写入数据被编程在存储单元阵列中; 和突发断电（SPO）检测电路，其中SPO检测电路包括：感测单元; 第一驱动器，被配置为向所述感测单元提供第一电压; 以及第二驱动器，被配置为向所述感测单元提供第二电压，其中所述感测单元的编程状态根据所述第一驱动器和所述第二驱动器被断电的顺序或时间差而变得不同。
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