公开(公告)号：US09812539B2

公开(公告)日：2017-11-07

申请号：US14962003

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Sung-In Kim ,  Jung-Woo Song ,  Jae-Rok Kahng ,  Dae-Won Kim

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66 ,  H01L21/768 ,  H01L21/74 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L21/285

CPC classification number: H01L29/4236 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/66621 ,  H01L43/08 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

公开(公告)号：US20160181385A1

公开(公告)日：2016-06-23

申请号：US14962003

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Sung-In KIM ,  Jung-Woo SONG ,  Jae-Rok KAHNG ,  Dae-Won KIM

IPC: H01L29/423 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L21/768 ,  H01L27/24 ,  H01L45/00 ,  H01L23/535 ,  H01L23/532 ,  H01L29/40 ,  H01L27/108 ,  H01L43/12

CPC classification number: H01L29/4236 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/66621 ,  H01L43/08 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

Abstract translation: 提供了包括限定栅极沟槽的衬底的半导体器件。 掩埋栅极结构设置在栅极沟槽中，并且至少填充栅极沟槽。 掩埋栅极结构包括栅极绝缘层图案，栅电极和覆盖层图案。 第一和第二杂质区域分别设置在与掩埋栅极结构相邻的衬底的部分处。 第一和第二杂质区域中的每一个的至少一部分面向掩埋栅极结构的侧壁。 第一和第二掩埋接触结构分别设置在第一和第二杂质区上。 第一和第二掩埋接触结构中的每一个包括金属硅化物图案和金属图案，并且第一和第二掩埋接触结构中的每一个的至少一部分面向掩埋栅极结构的侧壁。

公开(公告)号：US08993439B2

公开(公告)日：2015-03-31

申请号：US14285969

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Kil-Ho Lee ,  Ki-Joon Kim ,  Myoung-Su Son

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76807

Abstract: A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.

Abstract translation: 一种制造半导体器件的方法，包括形成模制层; 在成型层上形成镶嵌掩模层和掩模层; 通过蚀刻掩模层形成掩模层图案; 通过部分蚀刻镶嵌掩模层形成镶嵌图案; 在掩模层图案上形成镶嵌掩模层以埋藏镶嵌图案; 通过蚀刻镶嵌掩模层和掩模层图案形成部分地与镶嵌图案重叠的镶嵌图案; 通过去除由镶嵌图案暴露的掩模层图案的一部分来连接镶嵌图案和镶嵌图案; 在镶嵌掩模层上形成镶嵌掩模层，以埋藏镶嵌图案; 以及通过使用掩模层图案的剩余部分蚀刻镶嵌掩模层和模制层，在镶嵌图案之下形成沟槽。