公开(公告)号：US08835252B2

公开(公告)日：2014-09-16

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US09812539B2

公开(公告)日：2017-11-07

申请号：US14962003

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Sung-In Kim ,  Jung-Woo Song ,  Jae-Rok Kahng ,  Dae-Won Kim

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66 ,  H01L21/768 ,  H01L21/74 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L21/285

CPC classification number: H01L29/4236 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/66621 ,  H01L43/08 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

公开(公告)号：US20130344666A1

公开(公告)日：2013-12-26

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。