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公开(公告)号：US10470004B2
公开(公告)日：2019-11-05
申请号：US15767987
申请日：2016-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong-Tae Kim , Jae-Han Kim
Abstract: The present disclosure relates to a technology for a sensor network, machine to machine (M2M) communication, machine type communication (MTC), and Internet of things (IoT). The present disclosure may be utilized for an intelligent service (smart home, smart building, smart city, smart car or connected car, health care, digital education, retail business, security and a safety-related service, etc.) on the basis of the technology. A method for providing a push-to-talk (PTT) service in a communication system, which is proposed by an embodiment of the present disclosure, comprises the steps of: generating a file format including information associated with time points at which multiple pieces of data should be reproduced; and reproducing the multiple pieces of data on the basis of the file format.
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2.发明授权Split-gate type nonvolatile memory device, semiconductor device having split-type nonvolatile memory device embedded therein, and methods of forming the same 有权分离式非易失性存储装置，嵌有分离式非易失性存储装置的半导体装置及其形成方法公开(公告)号：US09082865B2
公开(公告)日：2015-07-14
申请号：US13743445
申请日：2013-01-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tea-Kwang Yu , Kwang-Tae Kim , Yong-Tae Kim , Bo-Young Seo , Yong-Kyu Lee , Hee-Seog Jeon
IPC: H01L29/78 , H01L29/788 , G11C16/04 , H01L29/10 , H01L27/115
CPC classification number: H01L29/788 , G11C16/0425 , G11C16/0441 , H01L27/11529 , H01L29/1083 , H01L29/1087 , H01L29/7885
Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.
Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。
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3.发明申请SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME 有权分离门型非易失性存储器件，具有嵌入式分离型非易失性存储器件的半导体器件及其形成方法公开(公告)号：US20130242659A1
公开(公告)日：2013-09-19
申请号：US13743445
申请日：2013-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tea-Kwang Yu , Kwang-Tae Kim , Yong-Tae Kim , Bo-Young Seo , Yong-Kyu Lee , Hee-Seog Jeon
IPC: H01L29/788 , G11C16/04
CPC classification number: H01L29/788 , G11C16/0425 , G11C16/0441 , H01L27/11529 , H01L29/1083 , H01L29/1087 , H01L29/7885
Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.
Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。
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