公开(公告)号：US09263588B2

公开(公告)日：2016-02-16

申请号：US14635034

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US09595612B2

公开(公告)日：2017-03-14

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US09184232B2

公开(公告)日：2015-11-10

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US20130320461A1

公开(公告)日：2013-12-05

申请号：US13960434

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US08913430B2

公开(公告)日：2014-12-16

申请号：US13955103

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

公开(公告)号：US20160155838A1

公开(公告)日：2016-06-02

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US09082865B2

公开(公告)日：2015-07-14

申请号：US13743445

申请日：2013-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

IPC: H01L29/78 ,  H01L29/788 ,  G11C16/04 ,  H01L29/10 ,  H01L27/115

CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

公开(公告)号：US20130242659A1

公开(公告)日：2013-09-19

申请号：US13743445

申请日：2013-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

IPC: H01L29/788 ,  G11C16/04

CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

公开(公告)号：US09847422B2

公开(公告)日：2017-12-19

申请号：US15290269

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US08969939B2

公开(公告)日：2015-03-03

申请号：US13960434

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/792 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。