公开(公告)号：US09082865B2

公开(公告)日：2015-07-14

申请号：US13743445

申请日：2013-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

IPC: H01L29/78 ,  H01L29/788 ,  G11C16/04 ,  H01L29/10 ,  H01L27/115

CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

公开(公告)号：US20130242659A1

公开(公告)日：2013-09-19

申请号：US13743445

申请日：2013-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tea-Kwang Yu ,  Kwang-Tae Kim ,  Yong-Tae Kim ,  Bo-Young Seo ,  Yong-Kyu Lee ,  Hee-Seog Jeon

IPC: H01L29/788 ,  G11C16/04

CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0441 ,  H01L27/11529 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7885

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract translation: 分闸式非易失性存储器件包括具有第一导电类型的半导体衬底，在半导体衬底中具有第二导电类型的深阱，在深阱中具有第一导电类型的阱阱，具有 口袋中的第二导电类型，源极线区域上的擦除栅极，以及顺序地堆叠在擦除栅极侧的阱上的第一浮置栅极和第一控制栅极。 口袋井通过深井与衬底电隔离，使得施加到口袋的负电压可能不会对形成在衬底上的其它器件的操作产生不利影响。

公开(公告)号：US20140217490A1

公开(公告)日：2014-08-07

申请号：US13803791

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Young Seo ,  Weon-Ho Park ,  Chang-Min Jeon ,  Yong-Sang Cho

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench.

Abstract translation: 在非易失性存储器件及其制造方法中，器件包括衬底，衬底中的沟槽和第一栅极图案，第一栅极图案包括第一底部栅极电极，第一底部栅电极在沟槽中具有第一部分，并且在第一 并相对于基板的上表面向上方突出。 包括第二栅电极的第二栅极图案在第一栅极图案的一侧的基板上，并与第一栅极图案绝缘。 在第一栅极图案的与第二栅极图案相对的一侧上存在杂质区域和沟槽的重叠部分。

公开(公告)号：US20160124674A1

公开(公告)日：2016-05-05

申请号：US14932883

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young Seo ,  Min-Jung Kim ,  Jung-Yup Kang ,  Sei-Jin Kim ,  Dong-Wook Suh ,  Sung-Hwan Yun

IPC: G06F3/06

CPC classification number: G06F12/02 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/0638 ,  Y02D10/13 ,  Y02D10/14

Abstract: Provided is a method and apparatus for controlling a plurality of memory devices. According to various embodiments of the present disclosure, there is provided an electronic device. The electronic device includes a first memory and a second memory, and a processor that is functionally connected with the first memory and the second memory. The processor is configured to determine at least one state associated with the electronic device, and allocate at least a partial area of one of the first memory and the second memory to at least some data of at least one process to be executed in the electronic device based on the at least one state. Other embodiments are possible.

Abstract translation: 提供了一种用于控制多个存储器件的方法和装置。 根据本公开的各种实施例，提供了一种电子设备。 电子设备包括第一存储器和第二存储器，以及与第一存储器和第二存储器功能性连接的处理器。 处理器被配置为确定与电子设备相关联的至少一个状态，并且将第一存储器和第二存储器之一的至少一部分区域分配给电子设备中要执行的至少一个处理的至少一些数据 基于至少一个状态。 其他实施例是可能的。

公开(公告)号：US08913430B2

公开(公告)日：2014-12-16

申请号：US13955103

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。