公开(公告)号：US11417659B2

公开(公告)日：2022-08-16

申请号：US17025272

申请日：2020-09-18

申请人： Samsung Electronics Co., Ltd.

发明人： Yong-hoon Son

IPC分类号： H01L27/108

摘要： Disclosed are semiconductor memory devices and methods of fabricating the same. The method including forming a mold structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate, patterning the mold structure to form a first trench that exposes a first inner sidewall of the mold structure, growing a vertical semiconductor layer in the first trench such that a vertical semiconductor layer covers the first inner sidewall, using the substrate as a seed to, patterning the mold structure to form a second trench that exposes a second inner sidewall of the mold structure, forming a plurality of recesses by selectively removing the second insulating layers from the mold structure through the second trench, and horizontally growing a plurality of horizontal semiconductor layers in corresponding recesses, using the vertical semiconductor layer as a seed may be provided.

公开(公告)号：US11502086B2

公开(公告)日：2022-11-15

申请号：US17038355

申请日：2020-09-30

申请人： Samsung Electronics Co., Ltd.

发明人： Yong-hoon Son ,  Jae Hoon Kim ,  Kwang-Ho Park ,  Seungjae Jung

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

摘要： A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US11315929B2

公开(公告)日：2022-04-26

申请号：US17038606

申请日：2020-09-30

申请人： Samsung Electronics Co., Ltd.

发明人： Seung Jae Jung ,  Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-hoon Son

IPC分类号： H01L27/108 ,  H01L27/13 ,  H01L25/18 ,  H01L27/12

摘要： A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

公开(公告)号：US10418374B2

公开(公告)日：2019-09-17

申请号：US15398081

申请日：2017-01-04

申请人： Samsung Electronics Co., Ltd.

发明人： Eun-young Lee ,  Yong-hoon Son ,  Jae-young Ahn

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/10 ,  H01L27/11565

摘要： A vertical memory device includes a plurality of stacked structures, at least one inter-structure layer, and a channel structure. The plurality of stacked structures comprises a plurality of gate electrodes and a plurality of insulation film patterns that are alternately and repeatedly stacked on a substrate. At least one inter-structure layer is positioned between the two stacked structures adjacent to each other from among the plurality of stacked structures. A channel structure penetrates the plurality of stacked structures and the at least one inter-structure layer, the channel structure extending in the first direction, the channel structure being connected to the substrate.