公开(公告)号：US12197254B2

公开(公告)日：2025-01-14

申请号：US18414713

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae Jung ,  Jeongeun Kim ,  Sanghoon Han ,  Byungsun Kim ,  Dongjun Oh

IPC: G06F1/16

Abstract: An electronic device includes a display, a housing, a glass panel provided on the display, and a shielding printed layer provided on a second surface of the glass panel in a region corresponding to a space between a side face of the electronic device and an edge of the display. The glass panel includes a flat portion and a curved portion, which includes a first region having a curvature of the curved portion, a second region perpendicular to the first region and covered by the shielding printed layer, and a chamfer region constructed between the first region and the second region. A ratio of a height of the chamfer region with respect to the first region and a length of the chamfer region with respect to the second region has a value in a range of 2 to 4.

公开(公告)号：US20220068859A1

公开(公告)日：2022-03-03

申请号：US17207242

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Eun-Ji Kim ,  Jong-Ho Moon ,  Hyoungyol Mun ,  Han-Sik Yoo ,  Kiseok Lee ,  Seungjae Jung ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L23/00 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

公开(公告)号：US11700723B2

公开(公告)日：2023-07-11

申请号：US17193739

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae Jung ,  Kwangho Park ,  Jaehoon Kim

IPC: H01L27/06 ,  H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

公开(公告)号：US20230178505A1

公开(公告)日：2023-06-08

申请号：US18050497

申请日：2022-10-28

Applicant: Samsung Electronics Co.. Ltd.

Inventor： KISEOK LEE ,  Hyungeun Choi ,  Gijae Kang ,  Keunnam Kim ,  Soobin Yim ,  Moonyoung Jeong ,  Seungjae Jung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L27/10805 ,  H01L27/10897 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.

公开(公告)号：US11437382B2

公开(公告)日：2022-09-06

申请号：US16916366

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Song ,  Jaehoon Kim ,  Kwangho Park ,  Yonghoon Son ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H01L27/108

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US11765905B2

公开(公告)日：2023-09-19

申请号：US17185168

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun Choi ,  Jong-ho Moon ,  Han-sik Yoo ,  Kiseok Lee ,  Sung-hwan Jang ,  Seungjae Jung ,  Euichul Jeong ,  Taehyun An ,  Sangyeon Han ,  Yoosang Hwang

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/20 ,  H10B41/40 ,  H10B43/10 ,  H10B43/20

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/40 ,  H10B43/10 ,  H10B43/20

Abstract: A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.

公开(公告)号：US12127396B2

公开(公告)日：2024-10-22

申请号：US17874512

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Song ,  Jaehoon Kim ,  Kwangho Park ,  Yonghoon Son ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H10B12/00

CPC classification number: H10B12/373 ,  H10B12/0387

Abstract: An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

公开(公告)号：US12010828B2

公开(公告)日：2024-06-11

申请号：US17382844

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae Jung ,  Kwang-Ho Park

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included.

公开(公告)号：US11880244B2

公开(公告)日：2024-01-23

申请号：US18110564

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjae Jung ,  Jeongeun Kim ,  Sanghoon Han ,  Byungsun Kim ,  Dongjun Oh

IPC: G06F1/16

CPC classification number: G06F1/1652 ,  G06F1/1626

Abstract: An electronic device includes a display, a housing, a glass panel provided on the display, and a shielding printed layer provided on a second surface of the glass panel in a region corresponding to a space between a side face of the electronic device and an edge of the display. The glass panel includes a flat portion and a curved portion, which includes a first region having a curvature of the curved portion, a second region perpendicular to the first region and covered by the shielding printed layer, and a chamfer region constructed between the first region and the second region. A ratio of a height of the chamfer region with respect to the first region and a length of the chamfer region with respect to the second region has a value in a range of 2 to 4.

公开(公告)号：US11871558B2

公开(公告)日：2024-01-09

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jae Hoon Kim ,  Kwang-ho Park ,  Seungjae Jung

IPC: H01L29/786 ,  H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

CPC classification number: H10B12/30 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/01 ,  H10B12/05 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.