公开(公告)号：US10192624B2

公开(公告)日：2019-01-29

申请号：US15495072

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Song ,  Se-heon Baek ,  Yong-sung Cho

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

公开(公告)号：US10366769B2

公开(公告)日：2019-07-30

申请号：US15810741

申请日：2017-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-sung Cho ,  Il-han Park ,  Jung-yun Yun ,  Youn-ho Hong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/30 ,  G11C16/08

Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.

公开(公告)号：US10600488B2

公开(公告)日：2020-03-24

申请号：US16186840

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Song ,  Se-heon Baek ,  Yong-sung Cho

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.