公开(公告)号：US20220399401A1

公开(公告)日：2022-12-15

申请号：US17826944

申请日：2022-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok Kwon ,  Youngsik Rho ,  Sangwon Park ,  Sungwhan Seo ,  Dongkyu Lee ,  Jaeyong Jeong

IPC: H01L27/24

Abstract: A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

公开(公告)号：US20210202496A1

公开(公告)日：2021-07-01

申请号：US16935607

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGWAN NAM ,  Yongseok Kwon ,  Hongsoo Jeon

IPC: H01L27/115 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit device includes; a peripheral circuit structure, a cell array structure including gate lines overlapping the peripheral circuit structure and disposed on the peripheral circuit structure in a vertical direction, a conductive plate interposed between the peripheral circuit structure and the cell array structure and including through holes, conductive lines spaced apart from the conductive plate with the cell array structure interposed between the conductive lines and the conductive plate, and through electrodes connected to the conductive lines and extending to the peripheral circuit structure through the cell array structure and the through holes. The through holes include a first through holes arranged along a first straight line extending in a first horizontal direction, and second through holes arranged along a second straight line extending in parallel with the first straight line and spaced apart from the first straight line in a second horizontal direction.