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    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD
    1.
    发明公开
    PROCESS PROXIMITY CORRECTION METHOD BASED ON MACHINE LEARNING, OPTICAL PROXIMITY CORRECTION METHOD INCLUDING THE SAME, AND METHOD OF MANUFACTURING MASK BY USING THE PROCESS PROXIMITY CORRECTION METHOD 审中-公开

    公开(公告)号：US20240319580A1

    公开(公告)日：2024-09-26

    申请号：US18529781

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeyong Jeong ,  Bonhyun Gu ,  Sooyong Lee

    IPC: G03F1/36 ,  G03F1/84

    CPC classification number: G03F1/36 ,  G03F1/84

    Abstract: The present disclosure relates to process proximity correction (PPC) methods based on machine learning (ML), optical proximity correction (OPC) methods, and mask manufacturing methods including the PPC methods. One example PPC method based on ML includes obtaining a pattern gauge-based bottom critical dimension (CD) and obtaining pattern gauge-based features from a first layout, performing a gauge clustering operation of grouping and classifying pattern gauges including similar features, calculating distribution parameters in a skew-normal distribution of the pattern gauge-based bottom CD in each cluster, performing ML between the distribution parameters and a feature in each cluster to generate a prediction ML model, predicting a distribution, a maximum limit, and a minimum limit of the pattern gauge-based bottom CD by using the prediction ML model, generating an after cleaning inspection (ACI) target including a maximum process window, and generating a second layout by performing an development inspection (ADI) retarget operation.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM
    3.
    发明公开
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240264934A1

    公开(公告)日：2024-08-08

    申请号：US18426975

    申请日：2024-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungho PARK ,  Insu kim ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F12/0882 ,  G06F13/1668 ,  G06F2212/7201

    Abstract: In some embodiments, the memory system for communicating with a host includes a non-volatile memory device storing first mapping information, a volatile memory device storing second mapping information, and a memory controller. The first mapping information indicates a relationship between a logical address and a portion of a first physical address. The first physical address indicates a location where user data is stored. The second mapping information indicates a second relationship between the logical address and a second physical address that corresponds to a remaining portion of the first physical address. The memory controller is configured to obtain a target logical address that has been received from the host, and determine, based on the second mapping information, a target second physical address mapped to the target logical address. The non-volatile memory device is configured to obtain a target first physical address by using the first mapping information.

    Non-volatile memory device and programming method thereof
    4.
    发明授权
    Non-volatile memory device and programming method thereof 有权

    公开(公告)号：US11164643B2

    公开(公告)日：2021-11-02

    申请号：US16686567

    申请日：2019-11-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsoo Kim ,  Wandong Kim ,  Jaeyong Jeong

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/26

    Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

    Nonvolatile memory system that erases memory cells when changing their mode of operation
    5.
    发明授权
    Nonvolatile memory system that erases memory cells when changing their mode of operation 有权

    公开(公告)号：US10115466B2

    公开(公告)日：2018-10-30

    申请号：US15687564

    申请日：2017-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

    IPC: G11C11/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

    Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

    Non-volatile memory device and related method of operation
    6.
    发明授权
    Non-volatile memory device and related method of operation 有权
    非易失性存储器件及相关操作方法

    公开(公告)号：US09576672B2

    公开(公告)日：2017-02-21

    申请号：US14617976

    申请日：2015-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeyong Jeong ,  Ju Seok Lee

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/34 ,  G11C16/24

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/3454

    Abstract: A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.

    Abstract translation: 非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列，连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。 控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元，并且读取对应于偶数和奇数列之一的存储器单元 的第二读取模式。 在第一读取模式下执行感测操作至少两次，并且在第二读取模式中执行一次感测操作。

    Non-volatile memory device, controller and memory system
    8.
    发明授权
    Non-volatile memory device, controller and memory system 有权

    公开(公告)号：US11763869B2

    公开(公告)日：2023-09-19

    申请号：US17549095

    申请日：2021-12-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

    Storage device for supporting multiple hosts and operation method thereof
    10.
    发明授权
    Storage device for supporting multiple hosts and operation method thereof 有权

    公开(公告)号：US11409469B2

    公开(公告)日：2022-08-09

    申请号：US17129185

    申请日：2020-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myung Hyun Jo ,  Youngwook Kim ,  Jinwoo Kim ,  Jaeyong Jeong

    IPC: G06F3/06 ,  G06F13/24

    Abstract: An operation method of a storage device including first and second physical functions respectively corresponding to first and second hosts includes receiving performance information from each of the first and second hosts, setting a first weight value corresponding to the first physical function and a second weight value corresponding to the second physical function, based on the received performance information, selecting one of a first submission queue, a second submission queue, a third submission queue, and a fourth submission queue based on an aggregated value table, the first and second submission queues being managed by the first host and the third and fourth submission queues are managed by the second host, processing a command from the selected submission queue, and updating the aggregated value table based on a weight value corresponding to the processed command from among the first and second weights and input/output (I/O) information of the processed command.

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