公开(公告)号：US20210408970A1

公开(公告)日：2021-12-30

申请号：US17227996

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan HONG ,  Youngsoo SOHN ,  Jeongdon IHM ,  Changhyun BAE ,  Yoochang SUNG

IPC: H03F1/26 ,  H03F3/19

Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.

公开(公告)号：US20220368328A1

公开(公告)日：2022-11-17

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jinhyeok BAEK ,  Yoochang SUNG ,  Changsik YOO ,  Jeongdon IHM

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US20250038134A1

公开(公告)日：2025-01-30

申请号：US18771142

申请日：2024-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbae KIM ,  Byounggug MIN ,  Yoochang SUNG

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes: a package substrate including upper pads, lower pads, and a first wiring layer electrically connecting first upper pads of the upper pads to first lower pads of the lower pads, respectively; a semiconductor chip disposed on the package substrate and electrically connected to the first upper pads; an encapsulant covering the semiconductor chip and at least a portion of the package substrate; a first conductive layer covering at least a portion of each of the encapsulant and the package substrate, wherein the first conductive layer is configured to apply a first voltage; a dielectric layer stacked on the first conductive layer; and a second conductive layer stacked on the dielectric layer, wherein the second conductive layer is configured to apply a second voltage.

公开(公告)号：US20230032415A1

公开(公告)日：2023-02-02

申请号：US17722805

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jaewoo JEONG ,  Kyungryun KIM ,  Yoochang SUNG ,  Changsik YOO

IPC: G11C7/10

Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.