公开(公告)号：US11508456B2

公开(公告)日：2022-11-22

申请号：US16685458

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Taewon Kim ,  Yoonna Oh

IPC: G11C8/00 ,  G11C29/44 ,  G11C11/4096 ,  G06F13/40 ,  G11C11/4091 ,  G11C11/408

Abstract: A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

公开(公告)号：US11527303B2

公开(公告)日：2022-12-13

申请号：US16890559

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

IPC: G11C29/00 ,  G06F11/20 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

公开(公告)号：US11094390B2

公开(公告)日：2021-08-17

申请号：US16795730

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

IPC: G11C29/18 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

公开(公告)号：US20210124659A1

公开(公告)日：2021-04-29

申请号：US16890559

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

IPC: G06F11/20 ,  G06F12/10 ,  G11C29/00 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

公开(公告)号：US10339042B2

公开(公告)日：2019-07-02

申请号：US15695060

申请日：2017-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonna Oh ,  Deok-Gu Yoon ,  Sanguhn Cha

IPC: G06F12/02 ,  G06F3/06 ,  G11C8/12 ,  G11C29/42 ,  G11C29/00 ,  G06F11/10 ,  G11C7/12 ,  G11C29/12 ,  G11C29/44

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

公开(公告)号：US20130311831A1

公开(公告)日：2013-11-21

申请号：US13790657

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonna Oh ,  Pil-Kyu Baek ,  Deok-Gu Yoon

IPC: G06F11/07

CPC classification number: G06F11/0766 ,  G01R31/287 ,  G11C29/006 ,  G11C29/56008 ,  G11C29/808 ,  G11C2029/5604

Abstract: A fault distribution generation system is provided. The fault distribution generation system comprises: a fail address mapping module which receives a fail bit map representing failures included in a semiconductor device as a plurality of pixels having a plurality of different failure levels and fail addresses for the failures included in the semiconductor device, and maps the fail addresses to each pixel of the fail bit map; a fault pattern analyzing module which receives information on each pixel to which the fail addresses are mapped from the fail address mapping module, analyzes the received information, and classifies the failures included in each pixel into predetermined fault patterns; and a fault distribution estimating module which estimates an occurrence probability distribution of the fault patterns according to the failure levels based on results of the classification of the fault pattern analyzing module.

Abstract translation: 提供故障分配生成系统。 故障分配生成系统包括：故障地址映射模块，其将表示半导体装置中包含的故障的故障位图映射为具有多个不同故障等级的多个像素，以及包含在所述半导体器件中的故障的故障地址，以及 将故障地址映射到故障位图的每个像素; 从故障地址映射模块接收关于失败地址映射的每个像素的信息的故障模式分析模块，分析所接收的信息，并将每个像素中包括的故障分类为预定的故障模式; 以及故障分布估计模块，其基于所述故障模式分析模块的分类结果，根据所述故障等级来估计所述故障模式的发生概率分布。

公开(公告)号：US11791014B2

公开(公告)日：2023-10-17

申请号：US18053498

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/20 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/88 ,  G06F11/2094 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18 ,  G06F2201/82

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

公开(公告)号：US20230069753A1

公开(公告)日：2023-03-02

申请号：US18053498

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yesin Ryu ,  Yoonna Oh ,  Hyunki Kim

IPC: G11C29/00 ,  G06F11/20 ,  G06F12/10 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

公开(公告)号：US11450396B2

公开(公告)日：2022-09-20

申请号：US17398434

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

IPC: G11C29/18 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

公开(公告)号：US20220020445A1

公开(公告)日：2022-01-20

申请号：US17398434

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungryun Kim ,  Yoonna Oh ,  Hohyun Shin ,  Jaeho Lee

IPC: G11C29/18 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.