公开(公告)号：US09349851B2

公开(公告)日：2016-05-24

申请号：US14140616

申请日：2013-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。

公开(公告)号：US20140191312A1

公开(公告)日：2014-07-10

申请号：US14140616

申请日：2013-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。