公开(公告)号：US08969971B2

公开(公告)日：2015-03-03

申请号：US14045034

申请日：2013-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  Y10S257/90

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract translation: 提供半导体器件。 半导体器件可以包括晶体管区域和电阻器区域。 晶体管区域可以包括栅极结构。 电阻器区域可以在绝缘层上包括绝缘层和电阻器结构。 栅极结构的顶表面和电阻器结构的顶表面可以是基本上共面的。

公开(公告)号：US20140191312A1

公开(公告)日：2014-07-10

申请号：US14140616

申请日：2013-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。

公开(公告)号：US08981489B2

公开(公告)日：2015-03-17

申请号：US14102736

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/24

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract translation: 提供了包括电阻器结构的半导体器件。 半导体器件可以包括有源区上的栅极结构，场区上的电阻结构以及栅结构上的第一层间绝缘层和电阻结构。 半导体器件还可以包括垂直穿透第一层间绝缘层并且与第一层间绝缘层和电阻器沟槽插塞上的电阻器结构和第二层间绝缘层接触的电阻器沟槽插塞。 此外，半导体器件可以包括垂直穿过第一和第二层间绝缘层并接触电阻器结构的电阻器接触插塞。

公开(公告)号：US20150028399A1

公开(公告)日：2015-01-29

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US20140167181A1

公开(公告)日：2014-06-19

申请号：US14102736

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/24

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract translation: 提供了包括电阻器结构的半导体器件。 半导体器件可以包括有源区上的栅极结构，场区上的电阻结构以及栅结构上的第一层间绝缘层和电阻结构。 半导体器件还可以包括垂直穿透第一层间绝缘层并且与第一层间绝缘层和电阻器沟槽插塞上的电阻器结构和第二层间绝缘层接触的电阻器沟槽插塞。 此外，半导体器件可以包括垂直穿过第一和第二层间绝缘层并接触电阻器结构的电阻器接触插塞。

公开(公告)号：US09515150B2

公开(公告)日：2016-12-06

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US09349851B2

公开(公告)日：2016-05-24

申请号：US14140616

申请日：2013-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。

公开(公告)号：US10439033B2

公开(公告)日：2019-10-08

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

公开(公告)号：US20170062579A1

公开(公告)日：2017-03-02

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

Abstract translation: 半导体器件可以包括在衬底中具有第一源极/漏极和第二源极/漏极的衬底。 第一欧姆接触图案可以在第一源极/漏极的最上表面中，其中第一欧姆接触图案包括与第一金属合金化的第一半导体。 第二欧姆接触图案可以在第二源极/漏极的最上表面中，其中第二欧姆接触图案包括与第一半导体不同的第二半导体，并且与不同于第一金属的第二金属合金化。

公开(公告)号：US20140167180A1

公开(公告)日：2014-06-19

申请号：US14045034

申请日：2013-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  Y10S257/90

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract translation: 提供半导体器件。 半导体器件可以包括晶体管区域和电阻器区域。 晶体管区域可以包括栅极结构。 电阻器区域可以在绝缘层上包括绝缘层和电阻器结构。 栅极结构的顶表面和电阻器结构的顶表面可以是基本上共面的。