公开(公告)号：US10403640B2

公开(公告)日：2019-09-03

申请号：US15933062

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

公开(公告)号：US20190074289A1

公开(公告)日：2019-03-07

申请号：US15933062

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.