公开(公告)号：US11637019B2

公开(公告)日：2023-04-25

申请号：US17393201

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Sun Hwang ,  Han Sol Seok ,  Hyun Ku Kang ,  Byoung Ho Kwon ,  Chung Ki Min

IPC: H01L21/3105 ,  H01L25/065 ,  H01L21/762 ,  H01L27/11582 ,  H01L29/06 ,  H01L27/11556 ,  H01L21/78

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

公开(公告)号：US11087990B2

公开(公告)日：2021-08-10

申请号：US16433218

申请日：2019-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Sun Hwang ,  Han Sol Seok ,  Hyun Ku Kang ,  Byoung Ho Kwon ,  Chung Ki Min

IPC: H01L27/11582 ,  H01L21/3105 ,  H01L25/065 ,  H01L21/762 ,  H01L29/06 ,  H01L27/11556 ,  H01L21/78

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

公开(公告)号：US20190074289A1

公开(公告)日：2019-03-07

申请号：US15933062

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

公开(公告)号：US10403640B2

公开(公告)日：2019-09-03

申请号：US15933062

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.