公开(公告)号：US20140021593A1

公开(公告)日：2014-01-23

申请号：US13785675

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Gwon Jang ,  Young-Lyong Kim ,  Ae-Nee Jang

IPC: H01L23/495

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L2224/16

Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.

Abstract translation: 半导体封装可以包括具有通孔的电路板芯片，安装在电路板芯片上的半导体器件和密封剂。 密封剂封装半导体器件，填充通孔并具有作为其中形成密封剂的模具的互补体的外部图案。 包装的一侧上的外部图案反映了模制形状，该模具形状相对于包装材料的相对侧上的密封剂材料流延迟封装材料的流动。

公开(公告)号：US10658300B2

公开(公告)日：2020-05-19

申请号：US16102391

申请日：2018-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Lyong Kim ,  Seung-Duk Baek

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.

公开(公告)号：US09024448B2

公开(公告)日：2015-05-05

申请号：US13785675

申请日：2013-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Gwon Jang ,  Young-Lyong Kim ,  Ae-Nee Jang

IPC: H01L23/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/13

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L2224/16

Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.

Abstract translation: 半导体封装可以包括具有通孔的电路板芯片，安装在电路板芯片上的半导体器件和密封剂。 密封剂封装半导体器件，填充通孔并具有作为其中形成密封剂的模具的互补体的外部图案。 包装的一侧上的外部图案反映了模制形状，该模具形状相对于包装材料的相对侧上的密封剂材料流延迟封装材料的流动。

公开(公告)号：US10804218B2

公开(公告)日：2020-10-13

申请号：US16110674

申请日：2018-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Lyong Kim ,  Seung-Duk Baek

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18

Abstract: A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.