公开(公告)号：US10749672B2

公开(公告)日：2020-08-18

申请号：US15585253

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heonsoo Lee ,  Jaechul Park ,  Jonghoon Shin ,  Youngjin Chung ,  Hong-Mook Choi

IPC: H04L9/08 ,  G06F12/06 ,  G06F13/40 ,  G06F21/78 ,  G06F12/14

Abstract: A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.

公开(公告)号：US11689205B2

公开(公告)日：2023-06-27

申请号：US17503802

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsuk Jang ,  Hanseok Kim ,  Jaehyun Park ,  Hobin Song ,  Jongshin Shin ,  Youngjin Chung

IPC: H04L1/20 ,  H04L25/03 ,  H03L7/08 ,  H03L7/081 ,  H04L1/00

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H04L1/0033 ,  H04L1/0036 ,  H04L1/203 ,  H04L25/03019 ,  H04L25/03885

Abstract: An integrated circuit may include a receiver configured to receive a first data signal based on an mth (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.

公开(公告)号：US11354453B2

公开(公告)日：2022-06-07

申请号：US16013993

申请日：2018-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingoo Heo ,  Jaechul Park ,  Youngjin Chung ,  Hong-Mook Choi

IPC: G06F21/78 ,  G06F12/14 ,  G06F21/60 ,  G06F21/85 ,  G06F21/71

Abstract: An encryption device includes a counter, an encryption/decryption unit, and a timer. The counter is configured to generate a first timestamp for a first time. The encryption/decryption unit is configured to concatenate security data and the first timestamp, encrypt the concatenated data into encryption data, transmit the encryption data to a memory device, and decrypt read data transmitted from the memory device into decryption data. The timer is configured to inform the counter and the encryption/decryption unit that a time elapses from the first time to a second time such that the counter generates a second timestamp for the second time and the encryption/decryption unit decrypts the read data into the decryption data. Checking logic implemented by the encryption device is configured to check whether a decryption timestamp of the decryption data is identical to the first timestamp.