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    Transceiver performing internal loopback test and operation method thereof
    2.
    发明授权
    Transceiver performing internal loopback test and operation method thereof 有权

    公开(公告)号：US11606113B2

    公开(公告)日：2023-03-14

    申请号：US17384991

    申请日：2021-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Younwoong Chung ,  Yungeun Nam ,  Jongshin Shin

    IPC: H04B1/40 ,  H04B17/19 ,  H03K19/00

    Abstract: Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.

    Hybrid clock and data recovery circuit and system including the same
    5.
    发明授权
    Hybrid clock and data recovery circuit and system including the same 有权
    混合时钟和数据恢复电路和系统包括相同

    公开(公告)号：US09356772B2

    公开(公告)日：2016-05-31

    申请号：US14489986

    申请日：2014-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hee Lee ,  Jongshin Shin ,  YoungKyun Jeong ,  Dongchul Choi ,  Jung-Hoon Chun

    IPC: H04L7/033 ,  H04L27/22

    CPC classification number: H04L7/033 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L27/22

    Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.

    Abstract translation: 时钟数据恢复电路包括：采样器，用于对输入的数据位进行采样;相位检测器，用于根据采样的输入数据产生边沿位置信号和极性信号;有限状态机，用于保存当前边沿位置状态;极性判定单元 产生极性反转信号以反转极性信号，增益控制器产生跟踪带宽信号;恢复环路，被配置为调整参考时钟的边沿偏移;以及位选择器，被配置为恢复输入数据。 时钟数据恢复电路在第一操作模式下具有第一等待时间，在第二操作模式下具有第二等待时间。 时钟数据恢复电路中的相位检测器可以包括第一相位检测器和第二检测器，其组合在一起，用于时钟数据恢复电路的低等待时间和低锁定时间。

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