公开(公告)号：US20240222330A1

公开(公告)日：2024-07-04

申请号：US18454278

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun YOON ,  Yunseok CHOI ,  Jongpa HONG

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16148 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17136 ,  H01L2224/17517 ,  H01L2224/32146 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/2064

Abstract: A semiconductor package includes a first semiconductor chip including first front connection pads on a first front surface, first rear connection pads and dummy pads on a first rear surface, and through-electrodes. The package includes a second semiconductor chip including second front connection pads and test pads on a second front surface, and a protective layer including openings exposing at least a portion of the second front connection pads and the test pads. The package includes bump structures electrically connecting the first rear connection pads and the second front connection pads, and an adhesive film surrounding at least a portion of each of the first rear connection pads, the dummy pads, and the bump structures. The dummy pads overlap the test pads in a direction perpendicular to the first rear surface, and a height of the dummy pads is greater than a height of the first rear connection pads.

公开(公告)号：US20240088003A1

公开(公告)日：2024-03-14

申请号：US18318827

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae SHIN ,  Youngbae KIM ,  Youngjun YOON ,  Jeongkyu HA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a film substrate; a plurality of wires on an upper surface of the film substrate; an upper insulating film covering the plurality of wires on the upper surface of the film substrate and defining a plurality of pad openings and a mounting region opening such that, the plurality of pad openings expose at least a portion of an outer lead bonding portion of the plurality of wires along at least one of the first side surface or the second side surface and the mounting region opening exposes at least a portion of an inner lead bonding portion of the plurality of wiring; a semiconductor chip bonded to and electrically connected to the exposed inner lead bonding portion, and at least one support pattern on a lower surface of the film substrate and extending in the first direction to overlap with the plurality of pad openings.