公开(公告)号：US20240234277A1

公开(公告)日：2024-07-11

申请号：US18464091

申请日：2023-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae SHIN ,  Jeong-Kyu Ha

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/11

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0655 ,  H05K1/111 ,  H01L2224/32137 ,  H01L2224/32225 ,  H01L2224/97 ,  H01L2924/182

Abstract: A semiconductor package includes a base film that has peripheral regions extending in a longitudinal direction and an inner region disposed between the peripheral regions and extending in the longitudinal direction. A unit film package is disposed on the inner region of the base film and is defined by a cut line. Dummy patterns are disposed on the peripheral regions of the base film and between the cut line and the opposite ends in the width direction. A first solder resist layer is disposed on the base film and covers the unit film package inside the cut line. In a plan view, the first solder resist layer extends in the width direction, runs across the cut line, and covers the dummy patterns.

公开(公告)号：US20230369265A1

公开(公告)日：2023-11-16

申请号：US18100859

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae SHIN

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/08 ,  H01L25/105 ,  H01L2224/02381 ,  H01L2224/08112 ,  H01L2924/15151 ,  H01L2924/182

Abstract: A film package includes a base film including peripheral regions on opposite ends of the base film in a width direction and extending in a lengthwise direction, an inner region between the peripheral regions and extending in the lengthwise direction, and sprocket holes provided on the peripheral regions at a regular interval in the lengthwise direction, and a unit film package provided on the base film and defined by a cut line, the unit film package including a mount region on the inner region and a connection region provided in the lengthwise direction from the mount region, the connection region extending from the inner region toward a location between the sprocket holes in the lengthwise direction.

公开(公告)号：US20240413071A1

公开(公告)日：2024-12-12

申请号：US18623666

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae SHIN ,  Jeong-Kyu HA

IPC: H01L23/498 ,  H01L23/00

Abstract: Provided is a semiconductor package including a film substrate including a sprocket hole, a semiconductor chip on the film substrate, interconnection lines connected to the semiconductor chip, a dummy pattern between the sprocket hole and the semiconductor chip, and a cutting pattern between the semiconductor chip and the dummy pattern, wherein the cutting pattern is spaced apart from the interconnection lines and the dummy pattern in a first direction.

公开(公告)号：US20240321712A1

公开(公告)日：2024-09-26

申请号：US18607849

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae SHIN

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A chip-on-film (COF) package including a base film having facing first and second surfaces; a first upper pattern on the first surface and extending in a first direction; second upper patterns on the first surface, the second upper patterns including inner patterns and outer patterns that are spaced apart from each other in the first direction; an upper insulating layer covering the first upper pattern and part of the second upper patterns; lower patterns on the second surface and electrically connecting the inner patterns to the outer patterns; and inner via plugs passing through the base film and electrically connecting the inner patterns of the second upper patterns to the lower patterns, wherein at least one inner pattern is electrically connected to the inner via plug in a region that is not covered by the upper insulating layer.

公开(公告)号：US20240088003A1

公开(公告)日：2024-03-14

申请号：US18318827

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae SHIN ,  Youngbae KIM ,  Youngjun YOON ,  Jeongkyu HA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a film substrate; a plurality of wires on an upper surface of the film substrate; an upper insulating film covering the plurality of wires on the upper surface of the film substrate and defining a plurality of pad openings and a mounting region opening such that, the plurality of pad openings expose at least a portion of an outer lead bonding portion of the plurality of wires along at least one of the first side surface or the second side surface and the mounting region opening exposes at least a portion of an inner lead bonding portion of the plurality of wiring; a semiconductor chip bonded to and electrically connected to the exposed inner lead bonding portion, and at least one support pattern on a lower surface of the film substrate and extending in the first direction to overlap with the plurality of pad openings.