公开(公告)号：US20240071845A1

公开(公告)日：2024-02-29

申请号：US18209286

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesun KIM ,  Yunseok CHOI ,  Youngbae KIM

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L22/32 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes: a redistribution layer including a plurality of conductive lines; a plurality of conductive vias each connected to at least one of the plurality of conductive lines; and a plurality of lower pads each connected to one of the plurality of conductive vias; a semiconductor chip on the redistribution layer; and a plurality of external connection terminals attached to the plurality of lower pads; and a plurality of electrical paths, wherein each of the plurality of electrical paths includes at least one of the plurality of conductive lines and at least one of the plurality of conductive vias. The plurality of electrical paths is configured for testing the plurality of conductive lines and the plurality of conductive vias and is connected to at least four of the external connection test terminals.

公开(公告)号：US20240088003A1

公开(公告)日：2024-03-14

申请号：US18318827

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae SHIN ,  Youngbae KIM ,  Youngjun YOON ,  Jeongkyu HA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes a film substrate; a plurality of wires on an upper surface of the film substrate; an upper insulating film covering the plurality of wires on the upper surface of the film substrate and defining a plurality of pad openings and a mounting region opening such that, the plurality of pad openings expose at least a portion of an outer lead bonding portion of the plurality of wires along at least one of the first side surface or the second side surface and the mounting region opening exposes at least a portion of an inner lead bonding portion of the plurality of wiring; a semiconductor chip bonded to and electrically connected to the exposed inner lead bonding portion, and at least one support pattern on a lower surface of the film substrate and extending in the first direction to overlap with the plurality of pad openings.

公开(公告)号：US20140061841A1

公开(公告)日：2014-03-06

申请号：US13956666

申请日：2013-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngbae KIM ,  Hyon-Chol KIM

IPC: H01L31/02

CPC classification number: H01L31/02 ,  H01L24/32 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package including a substrate including an epoxy-based material, an image sensor chip mounted on the substrate, and an attaching part provided between the substrate and the image sensor chip may be provided. The attaching part may include a first attaching part, and a second attaching part provided around the first attaching part. The first attaching part may achieve high reliability of the semiconductor package in association with the second attaching part. The second attaching part may include a material having a low rigidity. Thus, it is possible to reduce or prevent warpage of the image sensor chip from occurring. Due to the presence of the second attaching part, a plane coverage ratio of the first attaching part relative to the image sensor chip can be reduced. Thus, the warpage of the image sensor chip can be reduced or prevented more effectively.

Abstract translation: 可以提供包括包括环氧基材料的基板，安装在基板上的图像传感器芯片以及设置在基板和图像传感器芯片之间的附接部分的半导体封装。 安装部可以包括第一安装部和围绕第一安装部设置的第二安装部。 第一附接部件可以实现与第二附接部件相关联的半导体封装件的高可靠性。 第二安装部可以包括刚性低的材料。 因此，可以减少或防止图像传感器芯片的翘曲发生。 由于第二安装部的存在，可以减少第一安装部相对于图像传感器芯片的平面覆盖率。 因此，可以更有效地降低或防止图像传感器芯片的翘曲。

公开(公告)号：US20240079300A1

公开(公告)日：2024-03-07

申请号：US18242917

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae KIM

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor package is provided. The semiconductor package includes: a wiring board including a base substrate layer, and solder masks and a plurality of solder ball lands provided on the base substrate layer; a chip provided on and electrically connected to the wiring board; a molding layer provided on the chip and the wiring board; and a plurality of solder balls arranged on a lower surface of the wiring board and fused with the plurality of solder ball lands. The plurality of solder ball lands include a plurality of solder mask defined (SMD) type solder ball lands having side surfaces in contact with the solder masks, and a plurality of non-solder mask defined (NSMD) type solder ball lands that are separated from the solder masks to define an open area that exposes the base substrate layer.

公开(公告)号：US20160262264A1

公开(公告)日：2016-09-08

申请号：US14983517

申请日：2015-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngbae KIM

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0281 ,  H05K3/281 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2201/10128 ,  H05K2201/10136

Abstract: A connection substrate and a display device including the same are provided. The connection substrate includes a first conductive portion disposed on a tensile surface of a base film and having a first thickness, a second conductive portion disposed on a compressive surface of the base film and having a second thickness smaller than the second thickness, a first insulating layer disposed on the first conductive portion and a second insulating layer disposed on the second conductive portion. A distance from a top surface of the first conductive portion to a top surface of the first insulating layer is smaller than the first thickness.

Abstract translation: 提供了连接基板和包括该连接基板的显示装置。 连接基板包括设置在基膜的拉伸表面上并具有第一厚度的第一导电部分，设置在基膜的压缩表面上并具有小于第二厚度的第二厚度的第二导电部分，第一绝缘体 层，设置在第一导电部分上，第二绝缘层设置在第二导电部分上。 从第一导电部分的顶表面到第一绝缘层的顶表面的距离小于第一厚度。

公开(公告)号：US20240032195A1

公开(公告)日：2024-01-25

申请号：US18336096

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngbae KIM

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/118 ,  H05K1/111 ,  H05K1/189 ,  H05K1/028 ,  H05K2201/10128

Abstract: A film package includes a film substrate extending in a first direction and including a first side and a second side facing each other, the film substrate including a device region between the first side and the second side, and the film substrate including a reinforcing region adjacent to at least one side of the device region in a second direction, the second direction intersecting the first direction. The film package includes a semiconductor chip having an elongated rod shape, and the semiconductor chip on the device region of the film substrate in the first direction, interconnection patterns electrically connected to the semiconductor chip, the interconnection patterns comprising input patterns extending toward the first side on the film substrate, and output patterns extending toward the second side on the film substrate, and a protective layer on the film substrate to cover at least a portion of the interconnection patterns.

公开(公告)号：US20240213104A1

公开(公告)日：2024-06-27

申请号：US18223790

申请日：2023-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae KIM

IPC: H01L21/66 ,  G01R31/28 ,  H03K3/03

CPC classification number: H01L22/34 ,  G01R31/2831 ,  G01R31/2884 ,  H03K3/0315

Abstract: Provided is a semiconductor package, including a first semiconductor chip, and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes a test pattern, and wherein a frequency based on stress being exerted on the first semiconductor chip is measured based on the test pattern.

公开(公告)号：US20240071895A1

公开(公告)日：2024-02-29

申请号：US18353279

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seoeun KYUNG ,  Byung Ho KIM ,  Youngbae KIM ,  Hongwon KIM ,  Seokwon LEE ,  Jae-Ean LEE ,  Dahee KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/105 ,  H01L25/18 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package may include a lower redistribution layer including a lower wiring and a lower via, an embedded region on the lower redistribution layer, a core layer on the lower redistribution layer and including a core via, and an under bump structure including an under bump pad on a lower surface of the lower redistribution layer and an under bump via connecting the lower wiring and the under bump pad, the under bump pad may overlap the under bump via, the lower via, and the core via in a plan view, and the under bump via may be spaced apart from at least one of the lower via and the core via in the plan view.

公开(公告)号：US20200092989A1

公开(公告)日：2020-03-19

申请号：US16689403

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge LEE ,  Youngbae KIM

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

公开(公告)号：US20150088797A1

公开(公告)日：2015-03-26

申请号：US14496568

申请日：2014-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngbae KIM ,  Moongu JEON ,  Byunggeun LEE ,  Ahmad Muqeem SHERI ,  Hyunguk CHOI

IPC: G06N3/04 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: Example embodiments relate to a synapse circuit connecting neuron circuits by using two memristors so as to enhance symmetry, a neuromorphic circuit using the same, and a unit cell composing the neuromorphic circuit.

Abstract translation: 示例性实施例涉及通过使用两个忆阻器来连接神经元电路以增强对称性的神经元电路，使用其的神经元电路和构成神经形态电路的单元电池的突触电路。