公开(公告)号：US20220101889A1

公开(公告)日：2022-03-31

申请号：US17346212

申请日：2021-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghyun Ryu ,  Minsung Kil ,  Youngsang Cho

IPC: G11C5/14

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

公开(公告)号：US11502061B2

公开(公告)日：2022-11-15

申请号：US16592897

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsang Cho ,  Heeseok Lee ,  Yunhyeok Im ,  Moonseob Jeong

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

公开(公告)号：US11837581B2

公开(公告)日：2023-12-05

申请号：US17983487

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsang Cho ,  Heeseok Lee ,  Yunhyeok Im ,  Moonseob Jeong

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/5385 ,  H01L2225/06572

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

公开(公告)号：US11854648B2

公开(公告)日：2023-12-26

申请号：US17947301

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghyun Ryu ,  Minsung Kil ,  Youngsang Cho

IPC: G11C5/14

CPC classification number: G11C5/148

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

公开(公告)号：US11488640B2

公开(公告)日：2022-11-01

申请号：US17346212

申请日：2021-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghyun Ryu ,  Minsung Kil ,  Youngsang Cho

IPC: G11C5/14

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

公开(公告)号：US20230290701A1

公开(公告)日：2023-09-14

申请号：US18052187

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok Im ,  Youngsang Cho

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a first substrate, a semiconductor chip disposed on the first substrate, a mold layer disposed on the first substrate and at least partially covering the semiconductor chip, and a heat dissipation structure disposed on a first top surface of the semiconductor chip and in the mold layer. The heat dissipation structure covers an inner side surface of the mold layer. A surface roughness of the first top surface of the semiconductor chip is greater than a surface roughness of a side surface of the semiconductor chip, and a surface roughness of the inner side surface of the mold layer is greater than a surface roughness of a top surface of the mold layer. The heat dissipation structure includes voids therein.

公开(公告)号：US20230016511A1

公开(公告)日：2023-01-19

申请号：US17947301

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghyun Ryu ,  Minsung Kil ,  Youngsang Cho

IPC: G11C5/14

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

公开(公告)号：US11495578B2

公开(公告)日：2022-11-08

申请号：US17038946

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsang Cho

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L23/29 ,  H01L25/18 ,  H01L25/10 ,  H01L23/31 ,  H01L23/525 ,  H01L23/485

Abstract: A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m·K to approximately 20 W/m·K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

公开(公告)号：US11251102B2

公开(公告)日：2022-02-15

申请号：US17030092

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunhyeok Im ,  Youngsang Cho

IPC: H01L23/36 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor module may include a substrate including a first region and a second region, a first chip mounted in the first region, a second chip and passive devices mounted in the second region, and a heat dissipation layer being in contact with a top surface of the first chip. The heat dissipation layer may be provided on top surfaces and side surfaces of the first chip, the second chip and the passive devices.