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    METHOD AND DEVICE FOR TEMPERATURE DETECTION AND THERMAL MANAGEMENT BASED ON POWER MEASUREMENT
    2.
    发明申请
    METHOD AND DEVICE FOR TEMPERATURE DETECTION AND THERMAL MANAGEMENT BASED ON POWER MEASUREMENT 有权

    公开(公告)号：US20220136909A1

    公开(公告)日：2022-05-05

    申请号：US17366348

    申请日：2021-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungsu Kim ,  Yunhyeok Im ,  Inhwan Baek ,  Dongsuk Shin

    IPC: G01K7/42 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3296

    Abstract: The present disclosure provides a device and methods to control a temperature of an integrated circuit (IC). For example, a device may include a circuit (e.g., an IC), a power monitor, a temperature sensor, and a controller. In some examples, temperature may be estimated based on power measured by a dynamic power monitor (DPM). In some cases, the estimated temperatures may be corrected based on temperature sensed by a temperature sensor on the IC. The power may be measured in shorter time periods and/or more frequent time periods compared to a time periods that the temperature sensor senses temperature. Accordingly, the temperature of an IC may be detected and adjusted more frequently based on the power measurements, and the temperature estimates may be adjusted for accuracy based on sensed temperatures.

    Semiconductor package including composite molding structure
    3.
    发明授权
    Semiconductor package including composite molding structure 有权

    公开(公告)号：US11908774B2

    公开(公告)日：2024-02-20

    申请号：US17850504

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heeseok Lee ,  Yunhyeok Im

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/40

    CPC classification number: H01L23/481 ,  H01L23/3135 ,  H01L23/498 ,  H01L25/105 ,  H01L2023/4087 ,  H01L2225/1011 ,  H01L2225/1041

    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

    SEMICONDUCTOR PACKAGE HAVING A SYSTEM-IN-PACKAGE STRUCTURE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING A SYSTEM-IN-PACKAGE STRUCTURE 有权
    具有系统级封装结构的半导体封装

    公开(公告)号：US20140353813A1

    公开(公告)日：2014-12-04

    申请号：US14188917

    申请日：2014-02-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyol Park ,  Yunhyeok Im ,  Eon Soo Jang

    IPC: H01L23/34

    CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/38 ,  H01L23/4275 ,  H01L23/4334 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.

    Abstract translation: 半导体封装包括衬底。 下半导体芯片设置在基板上方。 上半导体芯片设置在下半导体芯片上。 在下半导体芯片的一端的下半导体芯片的顶表面被暴露。 设置在上半导体芯片上方的散热片。 模制层设置在基板和热块之间。 模制层被配置为密封下半导体芯片和上半导体芯片。 上部间隔件设置在下部半导体芯片和热塞之间。 上隔板设置在下半导体芯片的暴露表面上。

    Semiconductor package including composite molding structure
    10.
    发明授权
    Semiconductor package including composite molding structure 有权

    公开(公告)号：US11373933B2

    公开(公告)日：2022-06-28

    申请号：US17016115

    申请日：2020-09-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heeseok Lee ,  Yunhyeok Im

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/40

    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

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