公开(公告)号：US20220308920A1

公开(公告)日：2022-09-29

申请号：US17529854

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyeong Byeon ,  Jonglae Park ,  Hojin Kim ,  Gurnrack Moon ,  Daeyeong Lee ,  Youngtae Lee

IPC: G06F9/48

Abstract: A task scheduling method for a central processing unit (CPU) including a plurality of cores includes receiving a task processing request, obtaining first feedback data for the plurality of cores, obtaining second feedback data for an external intellectual property (IP) block outside the CPU, and assigning a task to at least one of the plurality of cores based on the first feedback data and the second feedback data.

公开(公告)号：US20210081027A1

公开(公告)日：2021-03-18

申请号：US16861383

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Youngtae Lee ,  Choonghoon Park ,  Hyunchul Seok ,  Kwanjin Jung

IPC: G06F1/3296 ,  G06F1/324

Abstract: Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.

公开(公告)号：US12111674B2

公开(公告)日：2024-10-08

申请号：US17720483

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choonghoon Park ,  Jong-Lae Park ,  Bumgyu Park ,  Youngtae Lee ,  Donghee Han

IPC: G06F1/26 ,  G05F1/46 ,  G05F1/66 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F15/78

CPC classification number: G05F1/66 ,  G05F1/462 ,  G06F1/3243 ,  G06F1/3296 ,  G06F15/7807

Abstract: An operating method of a system-on-chip (SoC) which includes a processor including a first core and a dynamic voltage and frequency scaling (DVFS) module and a clock management unit (CMU) for supplying an operating clock to the first core, the operating method including: obtaining a required performance of the first core; finding available frequencies meeting the required performance; obtaining information for calculating energy consumption for each of the available frequencies; calculating the energy consumption for each of the available frequencies, based on the information; determining a frequency, which causes minimum energy consumption, from among the available frequencies as an optimal frequency; and



adjusting an operating frequency to be supplied to the first core to the optimal frequency.

公开(公告)号：US11243806B2

公开(公告)日：2022-02-08

申请号：US16518159

申请日：2019-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Lae Park ,  Soohyun Kim ,  Youngtae Lee ,  Byung-Soo Kwon

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.

公开(公告)号：US20230071632A1

公开(公告)日：2023-03-09

申请号：US17720483

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHOONGHOON PARK ,  Jong-Lae Park ,  Bumgyu Park ,  Youngtae Lee ,  Donghee Han

IPC: G05F1/66 ,  G05F1/46 ,  G06F1/3296 ,  G06F1/3234 ,  G06F15/78

Abstract: An operating method of a system-on-chip (SoC) which includes a processor including a first core and a dynamic voltage and frequency scaling (DVFS) module and a clock management unit (CMU) for supplying an operating clock to the first core, the operating method including: obtaining a required performance of the first core; finding available frequencies meeting the required performance; obtaining information for calculating energy consumption for each of the available frequencies; calculating the energy consumption for each of the available frequencies, based on the information; determining a frequency, which causes minimum energy consumption, from among the available frequencies as an optimal frequency; and
adjusting an operating frequency to be supplied to the first core to the optimal frequency.

公开(公告)号：US11243604B2

公开(公告)日：2022-02-08

申请号：US16861383

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonglae Park ,  Youngtae Lee ,  Choonghoon Park ,  Hyunchul Seok ,  Kwanjin Jung

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/324

Abstract: Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.

公开(公告)号：US11768702B2

公开(公告)日：2023-09-26

申请号：US17112008

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Seok ,  Choonghoon Park ,  Byungsoo Kwon ,  Bumgyu Park ,  Jonglae Park ,  Junhwa Seo ,  Youngcheol Shin ,  Youngtae Lee

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/50 ,  G06F9/505 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/541 ,  G06F9/4893

Abstract: An apparatus and a method for scheduling a task in an electronic device including a heterogeneous multi-processor are provided. The electronic device includes a memory and a processor operatively connected to the memory and including a plurality of heterogeneous cores. The processor may be configured to identify, when a task to be scheduled occurs, a scheduling group having the task among a plurality of predefined scheduling groups, and to perform scheduling for the task, based on the identified scheduling group having the task and a priority of the task.

公开(公告)号：US20200151005A1

公开(公告)日：2020-05-14

申请号：US16518159

申请日：2019-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Lae Park ,  Soohyun Kim ,  Youngtae Lee ,  Byung-Soo Kwon

IPC: G06F9/48 ,  G06F9/50

Abstract: A scheduling method of a system on chip including a multi-core processor includes receiving a schedule-requested task, converting a priority assigned to the schedule-requested task into a linear priority weight, selecting a plurality of candidate cores, to which the schedule-requested task will be assigned, from among cores of the multi-core processor, calculating a preemption compare index indicating a current load state of each of the plurality of candidate cores, comparing the linear priority weight with the preemption compare index of the each of the plurality of candidate cores to generate a comparison result, and assigning the schedule-requested task to one candidate core of the plurality of candidate cores depending on the comparison result.