公开(公告)号：US20180143806A1

公开(公告)日：2018-05-24

申请号：US15634276

申请日：2017-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wook PARK ,  Bohdan KARPINSKYY ,  Yong Ki LEE ,  Yunhyeok CHOI ,  Mijung NOH

IPC: G06F7/58

CPC classification number: G06F7/582 ,  G06F7/588

Abstract: A random number generator may include a first meta-stable inverter having an input terminal and an output terminal connected to each other and configured to generate a meta-stable voltage, an amplifier configured to amplify the meta-stable voltage, control circuitry configured to adjust a threshold voltage of the meta-stable voltage, and a sampler configured to generate a random number based on sampling the meta-stable voltage. The random number generator may be configured to be operated according to different modes of operation of a plurality of modes of operation. The amplifier may be a second meta-stable inverter configured to amplify the meta-stable voltage or include an input terminal and an output terminal that are connected to each other based on the random number generator being operated according to a first mode of operation or a second mode of operation, respectively, of the plurality of modes of operation.

公开(公告)号：US20230025153A1

公开(公告)日：2023-01-26

申请号：US17867150

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok CHOI ,  Yongki LEE ,  Sumin NOH ,  Jieun PARK ,  Bohdan KARPINSKYY

IPC: G06F7/58

Abstract: A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.