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1.发明申请公开(公告)号：US20180143806A1
公开(公告)日：2018-05-24
申请号：US15634276
申请日：2017-06-27
发明人： Sang-Wook PARK , Bohdan KARPINSKYY , Yong Ki LEE , Yunhyeok CHOI , Mijung NOH
IPC分类号： G06F7/58
摘要： A random number generator may include a first meta-stable inverter having an input terminal and an output terminal connected to each other and configured to generate a meta-stable voltage, an amplifier configured to amplify the meta-stable voltage, control circuitry configured to adjust a threshold voltage of the meta-stable voltage, and a sampler configured to generate a random number based on sampling the meta-stable voltage. The random number generator may be configured to be operated according to different modes of operation of a plurality of modes of operation. The amplifier may be a second meta-stable inverter configured to amplify the meta-stable voltage or include an input terminal and an output terminal that are connected to each other based on the random number generator being operated according to a first mode of operation or a second mode of operation, respectively, of the plurality of modes of operation.
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公开(公告)号：US20230025153A1
公开(公告)日：2023-01-26
申请号：US17867150
申请日：2022-07-18
发明人： Yunhyeok CHOI , Yongki LEE , Sumin NOH , Jieun PARK , Bohdan KARPINSKYY
IPC分类号： G06F7/58
摘要： A random number generating circuit includes: an oscillation circuit including a plurality of first delay elements connected to each other in series to generate an oscillation signal; a sampling circuit including a plurality of second delay elements connected to each other in series to generate a plurality of sampling signals by sampling the oscillation signal at a plurality of sampling points in time based on the plurality of second delay elements; and a random number determining circuit configured to generate a random number based on a target sampling point in time associated with a target sampling signal in which a first logic level transition occurs from among the plurality of sampling signals, wherein the plurality of sampling points includes the target sampling point.
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公开(公告)号：US20200159497A1
公开(公告)日：2020-05-21
申请号：US16541705
申请日：2019-08-15
发明人： Ji-eun PARK , Yong-ki LEE , Yun-hyeok CHOI , Bohdan KARPINSKYY
摘要： A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.
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公开(公告)号：US20190068190A1
公开(公告)日：2019-02-28
申请号：US16004517
申请日：2018-06-11
发明人： Bohdan KARPINSKYY , Dae-hyeon KIM , Mi-jung NOH , Sang-wook PARK , Yong-ki LEE , Yun-hyeok CHOI
IPC分类号： H03K19/003 , H04L9/08 , H01L23/00
CPC分类号： H03K19/003 , G06F7/588 , H01L23/576 , H04L9/0866 , H04L9/0869 , H04L9/3278
摘要： An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.
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