公开(公告)号：US20250169052A1

公开(公告)日：2025-05-22

申请号：US18670998

申请日：2024-05-22

Applicant: Samsung electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Kangoh Yun

IPC: H10B12/00 ,  H10B41/41 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate structure including a substrate, first circuit devices on the substrate, second circuit devices that extend into the substrate, a gate isolation layer penetrating the substrate and between the second circuit devices, and a second substrate structure electrically connected to the first substrate structure on the first substrate structure, and including gate electrodes electrically connected to the first and second circuit devices. Adjacent second circuit devices among the second circuit devices are disposed symmetrically with respect to the gate isolation layer.

公开(公告)号：US11575009B2

公开(公告)日：2023-02-07

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon Baek ,  Taeyoung Kim ,  Hakseon Kim ,  Kangoh Yun ,  Changhoon Jeon ,  Junhee Lim

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

公开(公告)号：US20240196622A1

公开(公告)日：2024-06-13

申请号：US18514436

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangoh Yun ,  Sohyun Lee ,  Dongjin Lee ,  Junhee Lim

IPC: H10B43/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a substrate including an active region including a central active region extending in a first direction and first to fourth extended active regions extending from an edge of the central active region in a second direction perpendicular to the first direction, and a device isolation layer defining the active region; and first to fourth gate structures on the active region and spaced apart from one another, wherein the central active region, the first to fourth extended active regions, and the first to fourth gate structures constitute first to fourth pass transistors, the first to fourth pass transistors share one drain region on the central active region, and the active region has an H shape in a plan view.

公开(公告)号：US20250048639A1

公开(公告)日：2025-02-06

申请号：US18653301

申请日：2024-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon Kim ,  Kangoh Yun ,  Dongjin Lee ,  Youngrok Kim ,  Ryoongbin Lee ,  Jaeduk Lee

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A non-volatile memory device includes a peripheral circuit and a memory cell array that are sequentially stacked. The peripheral circuit includes, a device isolation layer defining an active region within a substrate, a first gate electrode extending in a first horizontal direction on the active region, an insulating pattern in a first recess and a second recess spaced apart in a second horizontal direction within the active region on opposing sides of the first gate electrode, a first low concentration doped region along an outer wall of the first recess, a second low concentration doped region along an outer wall of the second recess, a first source/drain region buried in the first low concentration doped region, and a second source/drain region buried in the second low concentration doped region.

公开(公告)号：US20230402454A1

公开(公告)日：2023-12-14

申请号：US18133977

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junhee Lim ,  Kangoh Yun ,  Sohyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76232

Abstract: A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.