公开(公告)号：US11575009B2

公开(公告)日：2023-02-07

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon Baek ,  Taeyoung Kim ,  Hakseon Kim ,  Kangoh Yun ,  Changhoon Jeon ,  Junhee Lim

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

公开(公告)号：US10651195B2

公开(公告)日：2020-05-12

申请号：US16168219

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20190312052A1

公开(公告)日：2019-10-10

申请号：US16232549

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Changseok Kang ,  Yongseok Kim ,  Junhee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.

公开(公告)号：US20250048627A1

公开(公告)日：2025-02-06

申请号：US18427977

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Heo ,  Kyoung-Ho Kim ,  Hojun Lee ,  Sungsu Moon ,  Sea Hoon Lee ,  Jaeduk Lee ,  Junhee Lim

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a substrate that has a recess region, a gate electrode on a bottom surface of the recess region, a gate dielectric layer between the gate electrode and the bottom surface of the recess region, a plurality of shield electrodes on laterally opposite sides of the gate electrode and on inner sidewalls of the recess region, a plurality of dielectric patterns between the shield electrodes and the inner sidewalls of the recess region, a plurality of impurity regions in the substrate and on opposite sides of the shield electrodes, and a channel region in the substrate and below the bottom surface of the recess region.

公开(公告)号：US20240324193A1

公开(公告)日：2024-09-26

申请号：US18515449

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MinKyung KIM ,  Hakseon Kim ,  Sunggil Kim ,  Jumi Bak ,  Kang-Oh Yun ,  Dongjin Lee ,  Sohyun Lee ,  Junhee Lim

IPC: H10B41/35 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/35 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06524

Abstract: A semiconductor device includes a substrate, a doped region on the substrate, the doped region including impurities of a first conductivity type at a first concentration, a gate structure on the substrate, and a first contact electrically connected to the doped region, the first contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including poly silicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type at a second concentration higher than the first concentration.

公开(公告)号：US10403719B2

公开(公告)日：2019-09-03

申请号：US15723694

申请日：2017-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Bongyong Lee ,  Junhee Lim

IPC: H01L27/00 ,  H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

公开(公告)号：US20230402454A1

公开(公告)日：2023-12-14

申请号：US18133977

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junhee Lim ,  Kangoh Yun ,  Sohyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76232

Abstract: A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.

公开(公告)号：US11557631B2

公开(公告)日：2023-01-17

申请号：US17088168

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Ilmok Park ,  Junhee Lim

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US11361798B2

公开(公告)日：2022-06-14

申请号：US16411106

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Junhee Lim ,  Hongsoo Kim ,  Chang-hoon Jeon

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10 ,  H01L27/1157 ,  G11C13/00 ,  G11C11/00 ,  H01L27/11582

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US10978480B2

公开(公告)日：2021-04-13

申请号：US16856663

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.