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公开(公告)号：US08854100B2
公开(公告)日：2014-10-07
申请号：US13601188
申请日：2012-08-31
IPC分类号： G06F1/04 , H03K3/00 , H03K19/003
CPC分类号： H03K19/003 , G06F1/10
摘要： A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
摘要翻译： 用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。 第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。 第一控制信号的有效边沿响应延迟的时钟信号的下降沿。 第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。 第二控制信号的有效边沿响应延迟的时钟信号的上升沿。
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公开(公告)号：US08710868B2
公开(公告)日：2014-04-29
申请号：US12974203
申请日：2010-12-21
IPC分类号： G11C7/00
CPC分类号： G11C7/065
摘要： A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
摘要翻译： 感测放大器单调器包括放大器电路和保持器电路。 当时钟信号处于第一阶段时，放大器电路输出预定的逻辑状态，并对数据信号进行采样，并且在时钟信号处于第二阶段时输出数据信号和互补逻辑状态中的至少一个数据信号 。 一旦数据信号在时钟信号处于第二阶段被采样时，数据信号的随后变化就不影响放大器电路的输出。 一旦在时钟信号处于第二阶段，数据信号被采样，保持器电路将保持采样数据信号的逻辑状态。 放大器电路可以接收多个数据信号，并且在时钟信号处于第二阶段时输出由选择信号选择的数据信号和/或互补值。
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公开(公告)号：US20140062564A1
公开(公告)日：2014-03-06
申请号：US13601175
申请日：2012-08-31
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
摘要翻译： 时钟驱动器电路提供具有根据提供给时钟驱动器的一个或多个控制信号确定的驱动强度的时钟信号，该时钟驱动器在运行时间内变化。 时钟驱动器以相关时钟网络的非谐振工作模式的第一驱动强度和相关时钟网络的谐振工作模式下的第二驱动强度操作，第一驱动强度高于第二驱动强度 驱动力。
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公开(公告)号：US08836403B2
公开(公告)日：2014-09-16
申请号：US13601175
申请日：2012-08-31
CPC分类号： G06F1/10
摘要： A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.
摘要翻译： 时钟驱动器电路提供具有根据提供给时钟驱动器的一个或多个控制信号确定的驱动强度的时钟信号，该时钟驱动器在运行时间内变化。 时钟驱动器以相关时钟网络的非谐振工作模式的第一驱动强度和相关时钟网络的谐振工作模式下的第二驱动强度操作，第一驱动强度高于第二驱动强度 驱动力。
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公开(公告)号：US20140062565A1
公开(公告)日：2014-03-06
申请号：US13601188
申请日：2012-08-31
IPC分类号： G06F1/04
CPC分类号： H03K19/003 , G06F1/10
摘要： A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
摘要翻译： 用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。 第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。 第一控制信号的有效边沿响应延迟的时钟信号的下降沿。 第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。 第二控制信号的有效边沿响应延迟的时钟信号的上升沿。
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公开(公告)号：US20120154188A1
公开(公告)日：2012-06-21
申请号：US12974203
申请日：2010-12-21
CPC分类号： G11C7/065
摘要： A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
摘要翻译： 感测放大器单调器包括放大器电路和保持器电路。 当时钟信号处于第一阶段时，放大器电路输出预定的逻辑状态，并对数据信号进行采样，并且在时钟信号处于第二阶段时输出数据信号和互补逻辑状态中的至少一个数据信号 。 一旦数据信号在时钟信号处于第二阶段被采样时，数据信号的随后变化就不影响放大器电路的输出。 一旦在时钟信号处于第二阶段，数据信号被采样，保持器电路将保持采样数据信号的逻辑状态。 放大器电路可以接收多个数据信号，并且在时钟信号处于第二阶段时输出由选择信号选择的数据信号和/或互补值。
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公开(公告)号：US20130166889A1
公开(公告)日：2013-06-27
申请号：US13334286
申请日：2011-12-22
申请人： Srikanth Arekapudi , Saurabh Gupta
发明人： Srikanth Arekapudi , Saurabh Gupta
CPC分类号： G06F9/30094 , G06F9/30032
摘要： A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.
摘要翻译： 描述了用于在处理器的执行流水线循环期间响应于处理数据生成标志的方法和装置。 处理器可以包括多路复用器，其被配置为根据指定的数据大小为接收的数据生成有效位，以及逻辑单元，被配置为基于移位或旋转操作命令来控制标志的生成，所指定的数据大小和指示多少字节的信息 以及用于旋转或移动数据的位。 可以使用进位标志来扩展由移位和旋转操作支持的位数。 符号标志可以用于指示结果是正数还是负数。 可以使用溢出标志来指示存在数据溢出，从而没有足够数量的位来存储数据。
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8.发明申请METHOD AND APPARATUS FOR ROTATING AND SHIFTING DATA DURING AN EXECUTION PIPELINE CYCLE OF A PROCESSOR 审中-公开在处理器的执行管道循环期间旋转和移动数据的方法和装置公开(公告)号：US20130151820A1
公开(公告)日：2013-06-13
申请号：US13315380
申请日：2011-12-09
申请人： Srikanth Arekapudi , Saurabh Gupta
发明人： Srikanth Arekapudi , Saurabh Gupta
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30018
摘要： A method and apparatus are described for processing data during an execution pipeline cycle of a processor. Valid bits of the data are generated according to a designated data size. Each of the valid bits is inserted into at least one of a plurality of bit positions. The valid bits are rotated in a predetermined direction (i.e., left or right rotation) by a designated number of bit positions. Valid bits are removed from a portion of the plurality of bit positions after being rotated. Zeros or most significant bits (MSBs) of the data may be inserted in the bit positions from which the valid bits were removed. The number of bit positions to rotate the valid bits by may be designated by a first bit subset and a second bit subset. The first bit subset may indicate a number of bytes, and the second bit subset may indicate a number of bits.
摘要翻译： 描述了用于在处理器的执行流水线周期期间处理数据的方法和装置。 根据指定的数据大小生成数据的有效位。 每个有效位被插入到多个位位置中的至少一个中。 有效位沿预定方向（即左旋转或右旋转）旋转指定数量的位位置。 有效位在旋转后从多个位位置的一部分移除。 可以将数据的零或最高有效位（MSB）插入从其中去除有效位的位位置。 旋转有效位的位位置的数量可以由第一位子集和第二位子集指定。 第一比特子集可以指示多个字节，并且第二比特子集可以指示多个比特。
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9.发明申请公开(公告)号：US20120291037A1
公开(公告)日：2012-11-15
申请号：US13107420
申请日：2011-05-13
IPC分类号： G06F9/46
CPC分类号： G06F9/3873 , G06F9/3012 , G06F9/3836 , G06F9/3855 , G06F9/3889
摘要： A method and processor are described for implementing programmable priority encoding to track relative age order of operations in a scheduler queue. The processor may comprise a scheduler queue configured to maintain an ancestry table including a plurality of consecutively numbered row entries and a plurality of consecutively numbered columns. Each row entry includes one bit in each of the columns. Pickers are configured to pick an operation that is ready for execution based on the age of the operation as designated by the ancestry table. The column number of each bit having a select logic value indicates an operation that is older than the operation associated with the number of the row entry that the bit resides in.
摘要翻译： 描述了一种用于实现可编程优先级编码以跟踪调度器队列中的操作的相对年龄顺序的方法和处理器。 处理器可以包括调度器队列，其被配置为维护包括多个连续编号的行条目和多个连续编号的列的祖先表。 每行条目在每列中包含一位。 选择器被配置为根据由祖先表指定的操作年龄来选择准备执行的操作。 具有选择逻辑值的每个位的列号指示比该位所在的行条目的数量更早的操作。
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10.发明申请AVOIDING BIST AND MBIST INTRUSION LOGIC IN CRITICAL TIMING PATHS 有权在关键时间表中避免BIST和MBIST INTRUSION LOGIC公开(公告)号：US20120124435A1
公开(公告)日：2012-05-17
申请号：US12948702
申请日：2010-11-17
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318536
摘要： Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.
摘要翻译： 提出了从微型电路设计的关键定时路径中去除BIST入侵逻辑的方法，系统和装置，而不会对测试产生重大影响。 在一个实施例中，BIST数据与扫描测试数据多路复用，并通过用于BIST测试的扫描测试单元串行计时。 在另一个实施例中，将BIST数据注入到一个或多个数据锁存器的反馈路径中。 在第三实施例中，将BIST数据注入执行单元内的多周期ALU的结果数据路径。 在每个实施例中，BIST电路从关键定时路径中消除。
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