公开(公告)号：US09379120B2

公开(公告)日：2016-06-28

申请号：US13947530

申请日：2013-07-22

申请人： SanDisk Technologies Inc.

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K Kai ,  Takashi W Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L21/764 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

公开(公告)号：US08946022B2

公开(公告)日：2015-02-03

申请号：US13774917

申请日：2013-02-22

申请人： SanDisk Technologies Inc.

发明人： Vinod Robert Purayath ,  James K Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L21/8247 ,  H01L21/762 ,  H01L21/28 ,  H01L29/788 ,  B82Y10/00 ,  H01L27/115

CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

摘要翻译： 基于纳米结构的电荷存储区域包括在非易失性存储器件中，并与制造选择栅极和外围电路集成。 在存储器阵列区域和外围电路区域上的衬底上施加一个或多个纳米结构涂层。 提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。 在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层，以选择性地在衬底的有源区上形成纳米结构。 自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。