公开(公告)号：US10020059B1

公开(公告)日：2018-07-10

申请号：US15486168

申请日：2017-04-12

Applicant: SanDisk Technologies LLC

Inventor： Muralikrishna Balaga ,  Vinayak Ghatawade ,  Aditya Pradhan

IPC: G11C16/06 ,  G11C16/12 ,  H03K19/00

CPC classification number: G11C16/12 ,  G11C7/1057 ,  G11C8/08 ,  G11C16/08 ,  G11C16/24 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K19/0005

Abstract: A memory device includes an electrical line operably coupled to a plurality of memory cells, and a switchable impedance driver operably coupled to the electrical line. An electronic circuit includes a first driver having a first output impedance, and a second driver having a second output impedance that is less than the first output impedance. The first driver and the second driver are operably coupled in parallel to an output of the electronic circuit. The electronic circuit includes logic circuitry to enable the second driver during switching of a digital output of the driver. A method includes driving an output with both the first driver and the second driver when an input switches between logic levels, and disabling the second driver when the output reaches a desired logic level following the switch between logic levels of the input.