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公开(公告)号：US12068051B2
公开(公告)日：2024-08-20
申请号：US17749813
申请日：2022-05-20
CPC分类号： G11C29/54 , G06F1/08 , G11C16/0483
摘要： Techniques for mitigating/eliminating the impact of duty distortion caused by delays in clock paths within a built-in high-frequency test circuit for NAND flash are disclosed. By mitigating or eliminating the impact of duty distortion, accuracy of the valid data window measurement is ensured. Rising edges of a strobe clock signal and an inverted strobe clock signal are used to respectively locate even and odd data (or vice versa) within an input buffer of the NAND flash during respective sweeps of the strobe and inverted strobe clock signals. In this manner, even if the strobe clock signal's duty ratio is distorted, there is no impact on the valid data window measurement. Further, read latency is used to introduce delay to a read enable (RE) clock signal, thereby obviating the need for a replica controlled delay in the RE clock path and eliminating the duty distortion that would otherwise occur.
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公开(公告)号：US12057189B2
公开(公告)日：2024-08-06
申请号：US17828921
申请日：2022-05-31
CPC分类号： G11C7/1039 , G11C7/106 , G11C7/1063 , G11C7/1087 , G11C7/109 , G11C7/222 , G11C8/10 , G11C8/12
摘要： A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.
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公开(公告)号：US20230386600A1
公开(公告)日：2023-11-30
申请号：US17828708
申请日：2022-05-31
摘要： Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
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公开(公告)号：US20230377677A1
公开(公告)日：2023-11-23
申请号：US17749813
申请日：2022-05-20
CPC分类号： G11C29/54 , G06F1/08 , G11C16/0483
摘要： Techniques for mitigating/eliminating the impact of duty distortion caused by delays in clock paths within a built-in high-frequency test circuit for NAND flash are disclosed. By mitigating or eliminating the impact of duty distortion, accuracy of the valid data window measurement is ensured. Rising edges of a strobe clock signal and an inverted strobe clock signal are used to respectively locate even and odd data (or vice versa) within an input buffer of the NAND flash during respective sweeps of the strobe and inverted strobe clock signals. In this manner, even if the strobe clock signal's duty ratio is distorted, there is no impact on the valid data window measurement. Further, read latency is used to introduce delay to a read enable (RE) clock signal, thereby obviating the need for a replica controlled delay in the RE clock path and eliminating the duty distortion that would otherwise occur.
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公开(公告)号：US20240071519A1
公开(公告)日：2024-02-29
申请号：US17898386
申请日：2022-08-29
CPC分类号： G06F3/0613 , G06F3/0635 , G06F3/0679 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32
摘要： The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.
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公开(公告)号：US11869619B2
公开(公告)日：2024-01-09
申请号：US17828708
申请日：2022-05-31
摘要： Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
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公开(公告)号：US20230395108A1
公开(公告)日：2023-12-07
申请号：US17832479
申请日：2022-06-03
CPC分类号： G11C7/222 , G11C7/109 , G11C7/1063 , G11C7/1039
摘要： Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.
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公开(公告)号：US12100458B2
公开(公告)日：2024-09-24
申请号：US17827562
申请日：2022-05-27
IPC分类号： G11C16/32
CPC分类号： G11C16/32
摘要： Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.
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公开(公告)号：US12020774B2
公开(公告)日：2024-06-25
申请号：US17832479
申请日：2022-06-03
CPC分类号： G11C7/222 , G11C7/1039 , G11C7/1063 , G11C7/109
摘要： Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.
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公开(公告)号：US20230386531A1
公开(公告)日：2023-11-30
申请号：US17828921
申请日：2022-05-31
CPC分类号： G11C7/1039 , G11C7/106 , G11C7/1063 , G11C7/1087 , G11C7/109 , G11C7/222
摘要： A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.
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