公开(公告)号：US10367493B1

公开(公告)日：2019-07-30

申请号：US16008640

申请日：2018-06-14

Applicant: SanDisk Technologies LLC

Inventor： Sravanti Addepalli ,  Ravindra Arjun Madpur ,  Sridhar Yadala

IPC: G11C7/22 ,  H03K5/156 ,  H03L7/089 ,  H03K5/133 ,  G06F1/08 ,  G06F1/10 ,  H03K5/00

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

公开(公告)号：US10361690B1

公开(公告)日：2019-07-23

申请号：US16008678

申请日：2018-06-14

Applicant: SanDisk Technologies LLC

Inventor： Sravanti Addepalli ,  Ravindra Arjun Madpur ,  Sridhar Yadala

IPC: H03K5/15 ,  H03K5/156 ,  G11C7/22 ,  H03L7/089 ,  G06F1/10 ,  G06F1/06 ,  H03K5/133 ,  H03K5/00

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.